Irfp250 Vishay Siliconix Footprint And Symbol Instructions

IRFP250

www.vishay.com

Vishay Siliconix

Power MOSFET

TO-247AC

N-Channel MOSFET

FEATURES

• Dynamic dV/dt rating
• Repetitive avalanche rated
• Isolated central mounting hole
• Fast switching
• Ease of Paralleling
• Simple drive requirements
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Note
* This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details

DESCRIPTION

Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness.
The TO-220AB package is universially preferred for commercial-industrial applications where higher power levels preclude the use of TO-220AB devices. The TO-247AC is similar but superior to the earlier TO-218 package because of its isolated mounting hole. It also provides greater creepage distance between pins to meet the requirements of most safety specifications.

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. V_DD = 50 V, starting T_J = 25 °C, L = 683 μH, R_g = 25 Ω, I_AS = 30 A (see fig. 12)
c. I_SD ≤ 30 A, dI/dt ≤ 190 A/μs, V_DD ≤ V_DS, T_J ≤ 150 °C
d. 1.6 mm from case

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER	SYMBOL	TEST CONDITIONS		MIN.	TYP.	MAX.	UNIT
Static
Drain-source breakdown voltage	VDS	VGS = 0 V, ID = 250 μA		200	–	–	V
VDS temperature coefficient	ΔVDS/TJ	Reference to 25 °C, ID = 1 mA		–	0.27	–	V/°C
Gate-source threshold voltage	VGS(th)	VDS = VGS, ID = 250 μA		2.0	–	4.0	V
Gate-source leakage	IGSS	VGS = ± 20 V		–	–	± 100	nA
Zero gate voltage drain current	IDSS	VDS = 200 V, VGS = 0 V		–	–	25	μA
		VDS = 160 V, VGS = 0 V, TJ = 125 °C		–	–	250
Drain-source on-state resistance	RDS(on)	VGS = 10 V	ID = 18 A b	–	–	0.085	Ω
Forward transconductance	gfs	VDS = 50 V, ID = 18 A		12	–	–	S
Dynamic
Input capacitance	Ciss	VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5		–	2800	–	pF
Output capacitance	Coss			–	780	–
Reverse transfer capacitance	Crss			–	250	–
Total gate charge	Qg	VGS = 10 V	ID = 30 A, VDS = 160 V, see fig. 6 and 13 b	–	–	140	nC
Gate-source charge	Qgs			–	–	28
Gate-drain charge	Qgd			–	–	74
Turn-on delay time	td(on)	VDD = 100 V, ID = 30 A, Rg = 6.2 Ω, RD = 3.2 Ω, see fig. 10 b		–	16	–	ns
Rise time	tr			–	86	–
Turn-off delay time	td(off)			–	70	–
Fall time	tf			–	62	–
Internal drain inductance	LD	Between lead, 6 mm (0.25″) from package and center of die contact		–	5.0	–	nH
Internal source inductance	LS			–	13	–
Drain-Source Body Diode Characteristics
Continuous source-drain diode current	IS	MOSFET symbol showing the integral reverse p – n junction diode		–	–	30	A
Pulsed diode forward current a	ISM			–	–	120
Body diode voltage	VSD	TJ = 25 °C, IS = 30 A, VGS = 0 V b		–	–	2.0	V
Body diode reverse recovery time	trr	TJ = 25 °C, IF = 30 A, dI/dt = 100 A/ms		–	360	540	ns
Body diode reverse recovery charge	Qrr			–	4.6	6.9	μC
Forward turn-on time	ton	Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 – Typical Output Characteristics, T_C = 25 °C

Fig. 2 – Typical Output Characteristics, T_C = 150 °C

Fig. 3 – Typical Transfer Characteristics

Fig. 4 – Normalized On-Resistance vs. Temperature

Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 – Typical Source-Drain Diode Forward Voltage

Fig. 8 – Maximum Safe Operating Area

Fig. 9 – Maximum Drain Current vs. Case Temperature

Fig. 10a – Switching Time Test Circuit

1. Pulse width ≤ 1 µs
   Duty factor ≤ 0.1 %

Fig. 10b – Switching Time Waveforms

Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 12a – Unclamped Inductive Test Circuit

1. Vary t_p to obtain required I_AS

Fig. 12b – Unclamped Inductive Waveforms

Fig. 12c – Maximum Avalanche Energy vs. Drain Current

Fig. 13a – Basic Gate Charge Waveform

Fig. 13b – Gate Charge Test

1. Current regulator
   Same type as D.U.T.
2. Current sampling resistors

Peak Diode Recovery dV/dt Test Circuit

1. Circuit layout considerations
   • Low stray inductance
   • Ground plane
   • Low leakage inductance current transformer
2. • dV/dt controlled by R_g
   • Driver same type as D.U.T.
   • I_SD controlled by duty factor “D”
   • D.U.T. – device under test

Fig. 14 – For N-Channel

Note
a. V_GS = 5 V for logic level devices

1. Driver gate drive
2. D.U.T. l_SD waveform
3. Reverse recovery current
4. D.U.T. V_DS waveform
5. Re-applied voltage
6. Inductor current
7. Body diode forward drop
8. Diode recovery
   dV/dt
9. Body diode forward current

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91212.

S22-0046, Rev. C, 24-Jan-2021          Document Number: 91212

Package Information

TO-247AC (High Voltage)

VERSION 1: FACILITY CODE = 9

Notes
(1) Package reference: JEDEC® TO247, variation AC
(2) All dimensions are in mm
(3) Slot required, notch may be rounded
(4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outermost extremes of the plastic body
(5) Thermal pad contour optional with dimensions D1 and E1
(6) Lead finish uncontrolled in L1
(7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm
(8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4 dimension at maximum material condition

VERSION 2: FACILITY CODE = Y

Lead Assignments

1. Gate
2. Drain
3. Source
4. Drain

1. Thermal pad
2. Planting
3. Base metal

Notes
(1) Dimensioning and tolerancing per ASME Y14.5M-1994
(2) Contour of slot optional
(3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured at the outermost extremes of the plastic body
(4) Thermal pad contour optional with dimensions D1 and E1
(5) Lead finish uncontrolled in L1
(6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154″)
(7) Outline conforms to JEDEC outline TO-247 with exception of dimension c

VERSION 3: FACILITY CODE = N

1. Base metal
2. Plating

Notes
(1) Dimensioning and tolerancing per ASME Y14.5M-1994
(2) Contour of slot optional
(3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured at the outermost extremes of the plastic body
(4) Thermal pad contour optional with dimensions D1 and E1
(5) Lead finish uncontrolled in L1
(6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154″)

Revision: 31-Oct-2022                  Document Number: 91360

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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Revision: 01-Jan-2023                 Document Number: 91000

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References

• applications.no
• vishay.com/doc?91000
• IRFP250 MOSFETs | Vishay