Vishay Irf9610 Siliconix Instructions

VISHAY IRF9610 Siliconix Instructions

PRODUCT SUMMARY

FEATURES

• Dynamic dV/dt rating
• P-channel
• Fast switching
• Ease of paralleling
• Simple drive requirements
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Note

• This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details.

DESCRIPTION

The power MOSFETs technology is the key to Vishay’s advanced line of Power MOSFET transistors. The efficient geometry and unique processing of the Power MOSFETs design achieve very low on-state resistance combined with high transconductance and extreme device ruggedness. The TO-220AB package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the TO-220AB contribute to its wide acceptance throughout the industry.

ORDERING INFORMATION

ABSOLUTE MAXIMUM RATINGS

(S (TC = 25 °C, unless otherwise noted)

Notes

• Repetitive rating; pulse width limited by maximum junction temperature (see fig. 5)
• Not applicable
• ISD ≤ -1.8 A, dI/dt ≤ 70 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
• 1.6 mm from cas

THERMAL RESISTANCE RATINGS 

SPECIFICATIONS

(TJ = 25 °C, unless otherwise noted)

PARAMETER	SYMBOL	TEST CONDITIONS		MIN.	TYP.	MAX.	UNIT
Static
Drain-source breakdown voltage	VDS	VGS = 0 V, ID = -250 μA		-200	–	–	V
VDS temperature coefficient	DVDS/TJ	Reference to 25 °C, ID = -1 mA		–	-0.23	–	V/°C
Gate-source threshold voltage	VGS(th)	VDS = VGS, ID = -250 μA		-2.0	–	-4.0	V
Gate-source leakage	IGSS	VGS = ± 20 V		–	–	± 100	nA
Zero gate voltage drain current	IDSS	VDS = -200 V, VGS = 0 V		–	–	-100	μA
		VDS = -160 V, VGS = 0 V, TJ = 125 °C		–	–	-500
Drain-source on-state resistance	RDS(on)	VGS = -10 V	ID = -0.90 A b	–	–	3.0	L
Forward transconductance	gfs	VDS = -50 V, ID = -0.90 A b		0.90	–	–	S
Dynamic
Input capacitance	Ciss	VGS = 0 V, VDS = -25 V,f = 1.0 MHz, see fig. 10		–	170	–	pF
Output capacitance	Coss			–	50	–
Reverse transfer capacitance	Crss			–	15	–
Total gate charge	Qg	VGS = -10 V	ID = -3.5 A, VDS = -160 V, see fig. 11 and 18 b	–	–	11	nC
Gate-source charge	Qgs			–	–	7.0
Gate-drain charge	Qgd			–	–	4.0
Turn-on delay time	td(on)	VDD = -100 V, ID = -0.90 A,Rg = 50 L, RD = 110 L, see fig. 17 b		–	8.0	–	ns
Rise time	tr			–	15	–
Turn-off delay time	td(off)			–	10	–
Fall time	tf			–	8.0	–
Gate input resistance	Rg	f = 1 MHz, open drain		2.5	–	14.3	L
Internal drain inductance	LD	Between lead, D6 mm (0.25″) from package and center of Guidie contactS		–	4.5	–	nH
Internal source inductance	LS			–	7.5	–
Drain-Source Body Diode Characteristics
Continuous source-drain diode current	IS	MOSFET symbol Showing the integral reverse   Gp – n junction diodeS		–	–	-1.8	A
Pulsed diode forward current a	ISM			–	–	-7.0
Body diode voltage	VSD	TJ = 25 °C, IS = -1.8 A, VGS = 0 V b		–	–	-5.8	V
Body diode reverse recovery time	trr	TJ = 25 °C, IF = -1.8 A, dI/dt = 100 A/μs b		–	240	360	ns
Body diode reverse recovery charge	Qrr			–	1.7	2.6	μC
Forward turn-on time	ton	Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes

• Repetitive rating; pulse width limited by maximum junction temperature (see fig. 5)
• Pulse width ≤ 300 μs; duty cycle ≤ 2 %

TYPICAL CHARACTERISTICS

(25 °C, unless otherwise noted)

Fig. 1 – Typical Output Characteristics

Fig. 2 – Typical Transfer Characteristics

Fig. 3 – Typical Saturation Characteristics

Fig. 4 – Maximum Safe Operating Area

Fig. 5 – Maximum Effective Transient Thermal Impedance, Junction-to-Case vs. Pulse Duration

Fig. 6 – Typical Transconductance vs. Drain Current

Fig. 7 – Typical Source-Drain Diode Forward Voltage

Fig. 8 – Breakdown Voltage vs. Temperature

Fig. 9 – Normalized On-Resistance vs. Temperature

Fig. 10 – Typical Capacitance vs. Drain-to-Source Voltage

Fig. 11 – Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 12 – Typical On-Resistance vs. Drain Current

Fig. 13 – Maximum Drain Current vs. Case Temperature

Fig. 14 – Power vs. Temperature Derating Curve

Fig. 15 – Clamped Inductive Test Circuit

Fig. 16 – Clamped Inductive Waveforms

Fig. 17a – Switching Time Test Circuit

Fig. 17b – Switching Time Waveforms

Fig. 18a – Basic Gate Charge Waveform

Fig. 18b – Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

Note

• Compliment N-Channel of D.U.T. for driver

Fig. 19 – For P-Channel

Note

• VGS = – 5 V for logic level and – 3 V drive devices

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91080.

Package Information

TO-220-1

Note

• M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM

Package Picture 

Disclaimer

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References

• Vishay Intertechnology
• vishay.com/doc?91000
• vishay.com/doc?99912