Vishay To-247ac Power Mosfet User Manual

VISHAY TO-247AC Power MOSFET

Power MOSFET

FEATURES

• Dynamic dV/dt rating
• Repetitive avalanche rated
• P-channel
• Isolated central mounting hole
• 175 °C operating temperature
• Fast switching
• Ease of paralleling
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Note

• This datasheet provides information about parts that are RoHS-compliant and/or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information/tables in this datasheet for details

DESCRIPTION

Third-generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance, and cost-effectiveness. The TO-247AC package is preferred for commercial-industrial applications where higher power levels preclude the use of TO-220AB devices. The TO-247AC is similar to but superior to the earlier TO-218 package because of its isolated mounting hole. It also provides greater creepage distance between pins to meet the requirements of most safety specifications.

Notes

• a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
• b. VDD = – 25 V, starting TJ = 25 °C, L = 3.3 mH, Rg = 25 Ω, IAS = – 21 A (see fig. 12)
• c. ISD ≤ – 21 A, dI/dt ≤ 200 A/μs, VDD ≤ VDS, TJ ≤ 175 °C
• d. 1.6 mm from the case

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER	SYMBOL	TEST CONDITIONS					MIN.	TYP.	MAX.	UNIT
Static
Drain-source breakdown voltage	VDS	VGS = 0 V, ID = -250 μA					-100	–	–	V
VDS temperature coefficient	DVDS/TJ	Reference to 25 °C, ID = -1 mA					–	-0.087	–	V/°C
Gate-source threshold voltage	VGS(th)	VDS = VGS, ID = -250 μA					-2.0	–	-4.0	V
Gate-source leakage	IGSS	VGS = ± 20 V					–	–	± 100	nA
Zero gate voltage drain current	IDSS	VDS = -100 V, VGS = 0 V					–	–	-100	μA
		VDS = -80 V, VGS = 0 V, TJ = 150 °C					–	–	-500
Drain-source on-state resistance	RDS(on)	VGS = -10 V	ID = – 13 Ab				–	–	0.20	W
Forward transconductance	gfs	VDS = -50 V, ID = – 13 Ab					6.2	–	–	S
Dynamic
Input capacitance	Ciss	VGS = 0 V, VDS = – 25 V, f = 1.0 MHz, see fig. 5					–	1400	–	pF
Output capacitance	Coss						–	590	–
Reverse transfer capacitance	Crss						–	140	–
Total gate charge	Qg	VGS = -10 V	ID = – 19 A, VDS = -80 V, see fig. 6 and 13 b				–	–	61	nC
Gate-source charge	Qgs						–	–	14
Gate-drain charge	Qgd						–	–	29
Turn-on delay time	td(on)	VDD = – 50 V, ID = -19 A, Rg = 9.1 W, RD = 2.4 W, see fig. 10 b					–	16	–	ns
Rise time	tr						–	73	–
Turn-off delay time	td(off)						–	34	–
Fall time	tf						–	57	–
Internal drain inductance	LD	Between lead,			D                   S		–	5.0	–
		6 mm (0.25″) from the package and center of the die contact		G						NH
Internal source inductance	LS						–	13	–
Drain-Source Body Diode Characteristics
Continuous source-drain diode current	IS	MOSFET symbol				D               S	–	–	– 21
		showing the integral reverse p – n junction diode		G						A
Pulsed diode forward current a	ISM						–	–	– 84
Body diode voltage	VSD	TJ = 25 °C, IS = – 21 A, VGS = 0 V b					–	–	– 5.0	V
Body diode reverse recovery time	trr	TJ = 25 °C, IF = – 19 A, dI/dt = 100 A/μs b					–	130	260	ns
Body diode reverse recovery charge	Qrr						–	0.35	0.70	μC
Forward turn-on time	ton	Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes

• a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
• b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %.

TYPICAL CHARACTERISTICS

(25 °C, unless otherwise noted)

• Fig. 1 – Typical Output Characteristics, TC = 25 °C
• Fig. 2 – Typical Output Characteristics, TC = 175 °C
• Fig. 3 – Typical Transfer Characteristics
• Fig. 4 – Normalized On-Resistance vs. Temperature
• Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
• Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
• Fig. 7 – Typical Source-Drain Diode Forward Voltage
• Fig. 8 – Maximum Safe Operating Area
• Fig. 9 – Maximum Drain Current vs. Case Temperature
• Fig. 10 – Switching Time Test Circuit
• Fig. 11 – Switching Time Waveforms
• Fig. 12 – Maximum Effective Transient Thermal Impedance, Junction-to-Case
• Fig. 13 – Unclamped Inductive Test Circuit
• Fig. 14 – Unclamped Inductive Waveforms
• Fig. 15 – Maximum Avalanche Energy vs. Drain Current
• Fig. 16 – Basic Gate Charge Waveform
• Fig. 17 – Gate Charge Test Circuit

Peak Diode Recovery DV/DT Test Circuit

Note

• Compliment N-Channel of D.U.T. for driver

1. Driver gate drive

• Note
  a. VGS = – 5 V for logic level and – 3 V drive devices
• Fig. 18 – For P-Channel

TO-247AC (High Voltage)

VERSION 1: FACILITY CODE = 9

Notes

1. Package reference: JEDEC® TO247, variation AC
2. All dimensions are in mm
3. Slot required, notch may be rounded
4. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at th e outermost extremes of the plastic body
5. Thermal pad contour optional with dimensions D1 and E1
6. Lead finish uncontrolled in L1
7. Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm
8. Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b 4 dimension at maximum material condition

VERSION 2: FACILITY CODE = Y

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994
2.  Contour of slot optional
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured a t the outermost extremes  of the plastic body
4. Thermal pad contour optional with dimensions D1 and E1
5. Lead finish uncontrolled in L1
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154″)
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c

VERSION 3: FACILITY CODE = N

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994
2. Contour of slot optional
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured a t the outermost extremes of the plastic body
4. Thermal pad contour optional with dimensions D1 and E1
5. Lead finish uncontrolled in L1
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154″)

Legal Disclaimer Notice

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© 2021 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED

• Revision: 19-Oct-2020
• For technical questions, contact: [email protected]
• THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND IN THIS DOCUMENT ARE
• SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
• Document Number: 91360

References

• Vishay Intertechnology
• vishay.com/doc?91000
• vishay.com/doc?99912
• IRFP9140 Power MOSFET | Vishay