Vishay Irlr024 Power Mosfet Owner's Manual

VISHAY IRLR024 Power MOSFET Owner’s Manual

Power MOSFET

N-Channel MOSFET

FEATURES

• Dynamic dV/dt rating
• Surface-mount (IRLR024, SiHLR024)
• Straight lead (IRLU024, SiHLU024)
• Available in tape and reel
• Logic-level gate drive
• RDS(on) specified at VGS = 4 V and 5 V
• Fast switching
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 

DESCRIPTION

Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness.

The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRLU, SiHLU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface-mount applications.

Note
a. See device orientation

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 25 V, starting TJ = 25 °C, L = 541 μH, Rg = 25 Ω, IAS = 14 A (see fig. 12)
c. ISD ≤ 17 A, dI/dt ≤ 140 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
e. When mounted on 1″ square PCB (FR-4 or G-10 material)

Note
a. When mounted on 1″ square PCB (FR-4 or G-10 material)

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER	SYMBOL	TEST CONDITIONS					MIN.	TYP.	MAX.	UNIT
Static
Drain-source breakdown voltage	VDS	VGS = 0 V, ID = 250 μA					60	–	–	V
VDS temperature coefficient	DVDS/TJ	Reference to 25 °C, ID = 1 mA					–	0.068	–	V/°C
Gate-source threshold voltage	VGS(th)	VDS = VGS, ID = 250 μA					1.0	–	2.0	V
Gate-source leakage	IGSS	VGS = ± 10 V					–	–	± 100	nA
Zero gate voltage drain current	IDSS	VDS = 60 V, VGS = 0 V					–	–	25	μA
		VDS = 48 V, VGS = 0 V, TJ = 125 °C					–	–	250
Drain-source on-state resistance	RDS(on)	VGS = 5.0 V	ID = 8.4 A b				–	–	0.10	L
		VGS = 4.0 V	ID = 7.0 A b				–	–	0.14
Forward transconductance	gfs	VDS = 25 V, ID = 8.4 A b					7.3	–	–	S
Dynamic
Input capacitance	Ciss	VGS = 0 V, VDS = 25 V,f = 1.0 MHz, see fig. 5					–	870	–	pF
Output capacitance	Coss						–	360	–
Reverse transfer capacitance	Crss						–	53	–
Total gate charge	Qg	VGS = 5.0 V	ID = 17 A, VDS = 48 V,see fig. 6 and 13 b				–	–	18	nC
Gate-source charge	Qgs						–	–	4.5
Gate-drain charge	Qgd						–	–	12
Turn-on delay time	td(on)	VDD = 30 V, ID = 17 A,Rg = 9.0 L, RD = 1.7 L, see fig. 10 b					–	11	–	ns
Rise time	tr						–	110	–
Turn-off delay time	td(off)						–	23	–
Fall time	tf						–	41	–
Internal drain inductance	LD	Between lead,6 mm (0.25″) from package and center of die contact		G	D S		–	4.5	–	nH
Internal source inductance	LS						–	7.5	–
Drain-Source Body Diode Characteristics
Continuous source-drain diode current	IS	MOSFET symbol showing the integral reversep – n junction diode		G		D S	–	–	14	A
Pulsed diode forward current a	ISM						–	–	56
Body diode voltage	VSD	TJ = 25 °C, IS = 14 A, VGS = 0 V b					–	–	1.5	V
Body diode reverse recovery time	trr	TJ = 25 °C, IF = 17 A, dI/dt = 100 A/μs b					–	130	260	ns
Body diode reverse recovery charge	Qrr						–	0.75	1.5	μC
Forward turn-on time	ton	Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 – Typical Output Characteristics, TC = 25 °C

Fig. 2 – Typical Output Characteristics, TC = 150 °C

Fig. 3 – Typical Transfer Characteristics

Fig. 4 – Normalized On-Resistance vs. Temperature

Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 – Typical Source-Drain Diode Forward Voltage

Fig. 8 – Maximum Safe Operating Area

Fig. 9 – Maximum Drain Current vs. Case Temperature

Fig. 10a – Switching Time Test Circuit

Fig. 10b – Switching Time Waveforms

Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 12a – Unclamped Inductive Test Circuit

Fig. 12b – Unclamped Inductive Waveforms

Fig. 12c – Maximum Avalanche Energy vs. Drain Current

Fig. 13a – Basic Gate Charge Waveform

Fig. 13b – Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

Fig. 14 – For N-Channel

VERSION 1: FACILITY CODE = Y

Note

• Dimension L3 is for reference only

VERSION 2: FACILITY CODE = N

Notes

• Dimensioning and tolerance confirm to ASME Y14.5M-1994
• All dimensions are in millimeters. Angles are in degrees
• Heat sink side flash is max. 0.8 mm
• Radius on terminal is optional

Case Outline for TO-251AA (High Voltage)

ECN: E21-0682-Rev. C, 27-Dec-2021
DWG: 5968

Notes

• Dimensioning and tolerancing per ASME Y14.5M-1994
• Dimension are shown in inches and millimeters
• Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005″) per side. These dimensions are measured at the outermost extremes of the plastic body
• Thermal pad contour optional with dimensions b4, L2, E1 and D1
• Lead dimension uncontrolled in L3
• Dimension b1, b3 and c1 apply to base metal only
• Outline conforms to JEDEC® outline TO-251AA

OPTION 2: FACILITY CODE = N

Notes

• Dimensioning and tolerancing per ASME Y14.5M-1994
• All dimension are in millimeters, angles are in degrees
• Heat sink side flash is max. 0.8 mm

RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)

Recommended Minimum Pads Dimensions in Inches/(mm)

Disclaimer

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For technical questions, contact: hvmos.[email protected]
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

References

• applications.no
• IRLR024, IRLU024, SiHLR024, SiHLU024 Power MOSFET | Vishay