Vishay Irfp350lcpbf N-channel Mosfet Instruction Manual

VISHAY IRFP350LCPbF N-Channel Mosfet

Product Information

Product Usage Instructions

1. Ensure that the product is properly mounted in the TO-247AC package.
2. Connect the drain (D), gate (G), and source (S) terminals of the MOSFET according to the desired circuit configuration.
3. Apply a suitable drain-source voltage (VDS) within the specified range (400 V with VGS = 10 V).
4. Control the gate-source voltage (VGS) to achieve the desired operating conditions.
5. Observe the maximum continuous drain current (ID) and maximum pulsed drain current (IDM) limits.
6. Ensure proper thermal management by considering the thermal resistance ratings:

Note: For detailed technical specifications and additional information, please refer to the product datasheet available at  www.vishay.com/doc?99912.

For any technical questions or support, please contact [email protected].

Power MOSFET

FEATURES

• Ultra low gate charge
• Reduced gate drive requirement
• Enhanced 30 VGS rating
• Reduced Ciss, Coss, Crss
• Isolated central mounting hole
• Dynamic dV/dt rated
• Repetitive avalanche rated
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Note 

• This datasheet provides information about parts that are  RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details

DESCRIPTION

This new series of low charge Power MOSFETs achieve significantly lower gate charge over conventional MOSFETs. Utilizing advanced MOSFETs technology the device improvements allow for reduced gate drive requirements, faster switching speeds and increased total system savings. These device improvements combined with the proven ruggedness and reliability of MOSFETs offer the designer a new standard in power transistors for switching applications.
The TO-247AC package is preferred for commercial-industrial applications where higher power levels preclude the use of TO-220AB devices. The TO-247AC is similar but superior to the earlier TO-218 package because of its isolated mounting hole.

Notes

• Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
• VDD = 25 V, starting TJ = 25 °C, L = 2.7 mH, Rg = 25 Ω, IAS = 16 A (see fig. 12)
• ISD ≤ 16 A, dI/dt ≤ 200 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
• 1.6 mm from case

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER	SYMBOL	TEST CONDITIONS		MIN.	TYP.	MAX.	UNIT
Static
Drain-source breakdown voltage	VDS	VGS = 0 V, ID = 250 μA		400	–	–	V
VDS temperature coefficient	DVDS/TJ	Reference to 25 °C, ID = 1 mA		–	0.49	–	V/°C
Gate-source threshold voltage	VGS(th)	VDS = VGS, ID = 250 μA		2.0	–	4.0	V
Gate-source leakage	IGSS	VGS = ± 20 V		–	–	± 100	nA
Zero gate voltage drain current	IDSS	VDS = 400 V, VGS = 0 V		–	–	25	μA
		VDS = 320 V, VGS = 0 V, TJ = 125 °C		–	–	250
Drain-source on-state resistance	RDS(on)	VGS = 10 V	ID = 9.6 A b	–	–	0.30	W
Forward transconductance	gfs	VDS = 50 V, ID = 9.6 A b		8.1	–	–	S
Dynamic
Input capacitance	Ciss	VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5		–	2200	–	pF
Output capacitance	Coss			–	390	–
Reverse transfer capacitance	Crss			–	31	–
Total Gate charge	Qg	VGS = 10 V	ID = 16 A, VDS = 320 V see fig. 6 and 13 b	–	–	76	nC
Gate-source charge	Qgs			–	–	20
Gate-drain charge	Qgd			–	–	37
Turn-on delay time	td(on)	VDD = 200 V, ID = 16 A, Rg = 6.2 W, RD = 12 W, see fig. 10 b		–	14	–	ns
Rise time	tr			–	54	–
Turn-off delay time	td(off)			–	33	–
Fall time	tf			–	35	–
Drain-Source Body Diode Characteristics
Continuous source-drain diode current	IS	MOSFET symbol Showing the integral reverse     p – n junction diode		–	–	16	A
Pulsed diode forward current a	ISM			–	–	64
Body diode voltage	VSD	TJ = 25 °C, IS = 16 A, VGS = 0 V b		–	–	1.6	V
Body diode reverse recovery time	trr	TJ = 25 °C, IF = 16 A, dI/dt = 100 A/μs b		–	440	660	ns
Body diode reverse recovery charge	Qrr			–	4.1	6.2	μC
Forward turn-on time	ton	Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes

• Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
• Pulse width ≤ 300 μs; duty cycle ≤ 2 %

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 – Typical Output Characteristics, TC = 25 °C

Fig. 2 – Typical Output Characteristics, TC = 150 °C

Fig. 3 – Typical Transfer Characteristics

Fig. 4 – Normalized On-Resistance vs. Temperature

Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 – Typical Source-Drain Diode Forward Voltage

Fig. 8 – Maximum Safe Operating Area

Fig. 9 – Maximum Drain Current vs. Case Temperature

Fig. 10 – Switching Time Test Circuit

Fig. 11 – Switching Time Waveforms

Fig. 12 – Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 13 – Unclamped Inductive Test Circuit

Fig. 14 – Unclamped Inductive Waveforms

Fig. 15 – Maximum Avalanche Energy vs. Drain Current

Fig. 16 – Basic Gate Charge Waveform

Fig. 17 – Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

Fig. 18 – For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91224.

TO-247AC (High Voltage)

VERSION 1: FACILITY CODE = 9

Notes

1. Package reference: JEDEC® TO247, variation AC
2. All dimensions are in mm
3. Slot required, notch may be rounded
4. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at th e outermost extremes of the plastic body
5. Thermal pad contour optional with dimensions D1 and E1
6. Lead finish uncontrolled in L1
7. Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm
8. Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b 4 dimension at maximum material condition

VERSION 2: FACILITY CODE = Y

Notes

• Dimensioning and tolerancing per ASME Y14.5M-1994
• Contour of slot optional
• Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured a t the outermost extremes of the plastic body
• Thermal pad contour optional with dimensions D1 and E1
• Lead finish uncontrolled in L1
• Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154″)
• Outline conforms to JEDEC outline TO-247 with exception of dimension c

VERSION 3: FACILITY CODE = N

Notes

• Dimensioning and tolerancing per ASME Y14.5M-1994
• Contour of slot optional
• Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005″) per side. These dimensions are measured a t the outermost extremes of the plastic body
• Thermal pad contour optional with dimensions D1 and E1
• Lead finish uncontrolled in L1
• Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154″)

Disclaimer

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References

• applications.no
• vishay.com/doc?91000
• IRFP350LC MOSFETs | Vishay