Intel Ug-20094 Cyclone 10 Gx Native Fixed Point Dsp Ip Core User Guide

intel UG-20094 Cyclone 10 GX Native Fixed Point DSP IP Core

Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide

The Intel Cyclone® 10 GX Native Fixed Point DSP IP core instantiates and controls a single Intel Cyclone 10 GX Variable Precision Digital Signal Processing (DSP) block. The Cyclone 10 GX Native Fixed Point DSP IP core is only available for Intel Cyclone 10 GX devices.

Cyclone 10 GX Native Fixed Point DSP IP Core Functional Block Diagram

Related Information
Introduction to Intel FPGA IP Cores.

Cyclone 10 GX Native Fixed Point DSP IP Core Features

The Cyclone 10 GX Native Fixed Point DSP IP core supports the following features:

• High-performance, power-optimized, and fully registered multiplication operations
• 18-bit and 27-bit word lengths
• Two 18 × 19 multipliers or one 27 × 27 multiplier per DSP block
• Built-in addition, subtraction, and 64-bit double accumulation register to combine multiplication results
• Cascading 19-bit or 27-bit when pre-adder is disabled and cascading 18-bit when pre-adder is used to form the tap-delay line for filtering application
• Cascading 64-bit output bus to propagate output results from one block to the next block without external logic support
• Hard pre-adder supported in 19-bit and 27-bit modes for symmetric filters
• Internal coefficient register bank in both 18-bit and 27-bit modes for filter implementation
• 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder

Getting Started

This chapter provides a general overview of the Intel FPGA IP core design flow to help you quickly get started with the Cyclone 10 GX Native Fixed Point DSP IP core. The Intel FPGA IP Library is installed as part of the Intel Quartus® Prime installation process. You can select and parameterize any Intel FPGA IP core from the library. Intel provides an integrated parameter editor that allows you to customize the Intel FPGA DSP IP core to support a wide variety of applications. The parameter editor guides you through the setting of parameter values and the selection of optional ports.

Related Information

• Introduction to Intel FPGA IP Cores
  Provides general information about all Intel FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores.
• Creating Version-Independent IP and Platform Designer (Standard) Simulatio Scripts
  Create simulation scripts that do not require manual updates for software or IP version upgrades.
• Project Management Best Practices
  Guidelines for efficient management and portability of your project and IP files.

Cyclone 10 GX Native Fixed Point DSP IP Core Parameter Settings

You can customize the Cyclone 10 GX Native Fixed Point DSP IP core by specifying the parameters using the parameter editor in the Intel Quartus Prime software.

Operation Mode Tab

Pre-adder Tab

Internal Coefficient Tab

Accumulator/Output Cascade Tab

Pipelining Tab

Maximum Input Data Width Per Operation Mode
You can customize the data width for x, y, and z inputs as specified in the table.

All pipeline input registers for dynamic control signals must have the same clock setting.

Functional Description

The Cyclone 10 GX Native Fixed Point DSP IP core consists of 2 architectures; 18 × 18 multiplication and 27 × 27 multiplication. Each instantiation of the Cyclone 10 GX Native Fixed Point DSP IP core generates only 1 of the 2 architectures depending on the selected operational modes. You can enable optional modules to your application.

Related Information
Variable Precision DSP Blocks in Intel Cyclone 10 GX Devices chapter, Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook.

Operational Modes

The Cyclone 10 GX Native Fixed Point DSP IP core supports 5 operational modes:

• The 18 × 18 Full Mode
• The 18 × 18 Sum of 2 Mode
• The 18 × 18 Plus 36 Mode
• The 18 × 18 Systolic Mode
• The 27 × 27 Mode

The 18 × 18 Full Mode
When configured as 18 × 18 full mode, the Cyclone 10 GX Native Fixed Point DSP IP core operates as two independent 18 (signed/unsigned) × 19 (signed) or 18
(signed/unsigned) × 18 (unsigned) multipliers with 37-bit output. This mode applies the following equations:

• resulta = ax * ay
• resultb = bx * by

The 18 × 18 Full Mode Architecture

The 18 × 18 Sum of 2 Mode
In 18 × 18 Sum of 2 modes, the Cyclone 10 GX Native Fixed Point DSP IP core enables the top and bottom multipliers and generates a result from addition or subtraction between the 2 multipliers. The sub-dynamic control signal controls an adder to perform the addition or subtraction operations. The resulta output width of the Cyclone 10 GX Native Fixed Point DSP IP core can support up to 64 bits when you enable accumulator/output cascade. This mode applies the equation of resulta =[±(ax * ay) + (bx * by)].

The 18 × 18 Sum of 2 Mode Architecture

The 18 × 18 Plus 36 Mode
When configured as 18 × 18 Plus 36 mode, the Cyclone 10 GX Native Fixed Point DSP IP core enables only the top multiplier. This mode applies the equation of resulta = (ax * ay) + concatenate(bx[17:0],by[17:0]).

The 18 × 18 Plus 36 Mode Architecture

You must set the Representation format for bottom multipliers y operand to unsigned when using this mode. When the input bus is less than 36-bit in this mode, you are required to provide the necessary signed extension to fill up the 36-bit input.

Using Less Than 36-bit Operand In 18 × 18 Plus 36 Mode
This example shows how to configure the Cyclone 10 GX Native Fixed Point DSP IP core to use 18 × 18 Plus 36 operational mode with a signed 12-bit input data of 101010101010 (binary) instead of a 36-bit operand.

1. Set Representation format for bottom multiplier x operand: to signed.
2. Set Representation format for bottom multiplier y operand: to unsigned.
3. Set ‘bx’ input bus width to 18.
4. Set ‘by’ input bus width to 18.
5. Provide data of ‘111111111111111111’ to bx input bus.
6. Provide data of ‘111111101010101010’ to by input bus.

The 18 × 18 Systolic Mode
In 18 × 18 systolic operational modes, the Cyclone 10 GX Native Fixed Point DSP IP core enables the top and bottom multipliers, an input systolic register for the top multiplier, and a chain systolic register for the chain in input signals. When you enable output cascade, this mode supports resulta output width of 44 bits. When you enable the accumulator feature without output cascade, you can configure the resulta output width to 64 bits.

The 18 × 18 Systolic Mode Architecture

The 27 × 27 Mode
When configured as 27 × 27 modes, the Cyclone 10 GX Native Fixed Point DSP IP core enables a 27(signed/unsigned) × 27(signed/unsigned) multiplier. The output bus can support up to 64 bits with accumulator/output cascade enabled. This mode applies the equation of resulta = ax * ay.

The 27 × 27 Mode Architecture

Optional Modules

The optional modules available in the Cyclone 10 GX Native Fixed Point DSP IP Core are:

• Input cascade
• Pre-adders
• Internal Coefficient
• Accumulator and output cascade
• Pipeline registers

Input Cascade
Input cascade feature is supported on ay and by input bus. When you set Enable input cascade for ‘ay’ input to Yes, the Cyclone 10 GX Native Fixed Point DSP IP core will take inputs from scan input signals instead of ay input bus. When you set Enable input cascade for ‘by’ input to Yes, the Cyclone 10 GX Native Fixed Point DSP IP core will take inputs from ay input bus instead of by input bus.

It is recommended to enable the input registers for ay and/or by whenever input cascade is enabled for the correctness of the application.

You can enable the delay registers to match the latency requirement between the input register and the output register. There are 2 delay registers in the core. The top delay register is used for ay or scan-in input ports while the bottom delay register is used for scanout output ports. These delay registers are supported in 18 × 18 full mode, 18 × 18 sums of 2 modes, and 18 × 18 systolic modes.

Pre-adder

The pre-adder can be configured in the following configurations:

• Two independent 18-bit (signed/unsigned) pre-adders.
• One 26-bit pre-adder.

When you enable pre-adder in 18 × 18 multiplication modes, ay and az are used as the input bus to the top pre-adder while by and bz are used as the input bus to the bottom pre-adder. When you enable pre-adder in 27 × 27 multiplication mode, ay and az are used as the input bus to the pre-adder. The pre-adder supports both addition and subtraction operations. When both pre-adders within the same DSP block are used, they must share the same operation type (either addition or subtraction).

Internal Coefficient
The internal coefficient can support up to eight constant coefficients for the multiplicands in 18-bit and 27-bit modes. When you enable the internal coefficient feature, two input buses to control the selection of the coefficient multiplexer will be generated. The coefsela input bus is used to select the predefined coefficients for the top multiplier and the counsel input bus is used to select the predefined coefficients for the bottom multiplier.

The internal coefficient storage does not support dynamically controllable coefficient values and external coefficient storage is required to perform such an operation.

Accumulator and Output Cascade

The accumulator module can be enabled to perform the following operations:

• Addition or subtraction operation
• Biased rounding operation using a constant value of 2N
• Dual channel accumulation

To dynamically perform addition or subtraction operation of the accumulator, control the negate input signal. For a biased rounding operation, you can specify and load a preset constant of 2N before the accumulator module is enabled by specifying an integer to the parameter N value of the preset constant. The integer N must be less than 64. You can dynamically enable or disable the use of the preset constant by controlling the loadconst signal. You can use this operation as an active muxing of the round value into the accumulator feedback path. The loaded cost and the accumulated signal usage is mutually exclusive.

You can enable the double accumulator register using the parameter Enable double accumulator to perform double accumulation. The accumulator module can support the chaining of multiple DSP blocks for addition or subtraction operations by enabling the chaining input port and chain-out output port. In 18 × 18 systolic mode, only 44-bit of the chain input bus and chain out output bus will be used. However, all 64-bit chains in the input bus must be connected to the chain-out output bus from the preceding DSP block.

Pipeline Register

The Cyclone 10 GX Native Fixed Point DSP IP core supports a single level of pipeline register. The pipeline register supports up to three clock sources and one asynchronous clear signal to reset the pipeline registers. There are five pipeline registers:

• data input bus pipeline register
• sub dynamic control signal pipeline register
• negate dynamic control signal pipeline register
• accumulate dynamic control signal pipeline register
• loadconst dynamic control pipeline register

You can choose to enable each data input bus pipeline registers and the dynamic control signal pipeline registers independently. However, all enabled pipeline registers must use the same clock source.

Clocking Scheme

The input, pipeline, and output registers in the Cyclone 10 GX Native Fixed Point DSP IP core supports three clock sources/enables and two asynchronous clears. All input registers use aclr[0] and all pipeline and output registers use aclr[1]. Each register type can select one of the three clock sources and clock enable signals. When you configure the Cyclone 10 GX Native Fixed Point DSP IP core to 18 × 18 systolic operation mode, the Intel Quartus Prime software will set the input systolic register and the chain systolic register clock source to the same clock source as the output register internally.

When you enable the double accumulator feature, the Intel Quartus Prime software will set the double accumulator register clock source to the same clock source as the output register internally.

Clocking Scheme Constraints
This tab shows the constraints you must apply for all the register clocking schemes.

Cyclone 10 GX Native Fixed Point DSP IP Core Signals

The following figure shows the input and output signals of the Cyclone 10 GX Native Fixed Point DSP IP core.

Cyclone 10 GX Native Fixed Point DSP IP Core Signals

Data Input Signals

Data Output Signals

Clock, Enable, and Clear Signals

Dynamic Control Signals

Internal Coeficient Signals

Input Cascade Signals

Output Cascade Signals

Document Revision History for the Cyclone 10 GX Native Fixed Point DSP IP Core User Guide

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References

• 1. Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide
• Intel® Quartus® Prime Software User Guides
• 1. Introduction to Intel® FPGA IP Cores
• 1. Introduction to Intel® FPGA IP Cores
• 1. Logic Array Blocks and Adaptive Logic Modules in Intel® Cyclone®...
• Intel ISO 9001:2015 Registrations