On Semiconductor Fdbl0200n100 Mosfet N-channel Power Trench Owner's Manual

On Semiconductor Fdbl0200n100 Mosfet N-channel Power Trench Owner's Manual

ON logo 1ON logoON logo 2FDBL0200N100 MOSFET N-Channel Power Trench
Owner’s Manual
www.onsemi.com
ON Semiconductor FDBL0200N100 MOSFET N-Channel Power Trench 1

FDBL0200N100 MOSFET N-Channel Power Trench

100 V, 300 A, 2.0 mΩ
FDBL0200N100

Features

  • Typical RDS(on) = 1.5 mΩ at VGS = 10 V, ID = 80 A
  • Typical Qg(tot) = 95 nC at VGS = 10 V, ID = 80 A
  • UIS Capability
  • This Device is Pb−Free and is RoHS Compliant

Applications

  • Industrial Motor Drive
  • Industrial Power Supply
  • Industrial Automation
  • Battery Operated Tools
  • Battery Protection
  • Solar Inverters
  • UPS and Energy Inverters
  • Energy Storage
  • Load Switch
VDSSRDS(ON) MAXID MAX
100 V2.0 mΩ @ 10 V300 A

ON Semiconductor FDBL0200N100 MOSFET N-Channel Power TrenchH−PSOF8L 11.68×9.80
CASE 100CU

MARKING DIAGRAM

ON Semiconductor FDBL0200N100 MOSFET N-Channel Power Trench fig 8

$Y = ON Semiconductor Logo
&Z = Assembly Plant Code
&3 = 3−Digit Plant Code
&K = 2−Digits Lot Run Traceability Code
FDBL0200N100 = Specific Device Code

ORDERING INFORMATION

See detailed ordering and shipping information on page 7 of this data sheet.
FDBL0200N100
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)

SymbolRatingValueUnit
VDSSDrain−to−Source Voltage100V
VGSGate−to−Source Voltage±20V
IDDrain Current − Continuous (VGS = 10) (Note 1)TC = 25°C300A
Pulsed Drain CurrentTC = 25°CSee Figure 4
EASSingle Pulse Avalanche Energy (Note 2)352mJ
PDPower Dissipation429W
Derate Above 25°C2.9W/°C
TJ, TSTGOperating and Storage Temperature−55 to +175°C
RθJCThermal Resistance, Junction to Case (Note 3)0.35° C/W
RθJAThermal Resistance, Junction to Ambient (Note 3a)43° C/W
RθJAThermal Resistance, Junction to Ambient (Note 3b)62.5° C/W

Stresses exceeding those listed in the Maximum Rating table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

  1. Current is limited by
  2. Starting TJ = 25°C, L = 1 mH, IAS = 84 A, VDD = 100 V during inductor charging and VDD = 0 V during time in avalanche.
  3. RθJAis the sum of the junction−to−case and case−to−ambient thermal resistance, where the case thermal reference is defined as the solder mounting surface of the drain RθJC is guaranteed by design, while RθJA is determined by the board design.
    1. 43°C/W when mounted on a 1 in2 pad of 2 oz copper
    2. 5°C/W when mounted on a minimum pad of 2 oz copper

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

SymbolParameterTest ConditionMinTypMaxUnit

OFF CHARACTERISTICS

BVDSSDrain−to−Source Breakdown VoltageID = 250 µA, VGS = 0 V100V
IDSSDrain−to−Source Leakage CurrentVDS = 100 V, VGS = 0VTJ = 25°C5µA
TJ = 175°C (Note 4)2mA
IGSSGate−to−Source Leakage CurrentVGS = ±20V±100nA

ON CHARACTERISTICS

VGS(th)Gate to Source Threshold VoltageVGS = VDS, ID = 250mA2.03.14.5V
RDS(on)Drain to Source On ResistanceID = 80A, VGS= 10VTJ = 25°C1.52.0
TJ = 175°C (Note 4)3.34.3

DYNAMIC CHARACTERISTICS

CissInput CapacitanceVDS = 50 V, VGS = 0 V, f = 1 MHz69709760pF
CossOutput Capacitance39505530pF
CrssReverse Transfer Capacitance2941pF
RgGate Resistancef = 1 MHz0.451Ω
Qg(ToT)Total Gate Charge at 10 VVGS = 0 to 10 V, VDD = 80 V, ID = 80 A95133nC
Qg(th)Threshold Gate ChargeVGS = 0 to 2 V, VDD = 80 V, ID = 80 A13nC
QgsGate−to−Source Gate ChargeVDD = 80 V, ID = 80 A31nC
QgdGate−to−Drain “Miller“ Charge20nC

SWITCHING CHARACTERISTICS

tonTurn−On TimeVDD = 50 V, ID = 80 A,
VGS = 10 V, RGEN = 6 Ω
73ns
td(on)Turn−On Delay3150ns
trRise Time2540ns
td(off)Turn−Off Delay3658ns
tfFall Time918ns
toffTurn−Off Time59ns

DRAIN−SOURCE DIODE CHARACTERISTICS

VSDSource−to−Drain Diode VoltageISD = 80 A, VGS = 0 V1.25V
ISD = 40 A, VGS = 0 V1.2V
trrReverse−Recovery TimeIF = 80 A, USD/DT = 100 A/µs, VDD = 80 V115184ns
QrrReverse−Recovery Charge172273nC

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions

TYPICAL CHARACTERISTICS

ON Semiconductor FDBL0200N100 MOSFET N-Channel Power Trench fig 7ON Semiconductor FDBL0200N100 MOSFET N-Channel Power Trench fig 6ON Semiconductor FDBL0200N100 MOSFET N-Channel Power Trench fig 5

ORDERING INFORMATION

DeviceDevice MarkingPackage TypeReel SizeTape WidthShipping
FDBL0200N100FDBL0200N100H−PSOF8L 11.68×9.80 (Pb−Free)13”24 mm2000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

H−PSOF8L 11.68×9.80
CASE 100CU ISSUE B
DATE 20 MAY 2022

ON Semiconductor FDBL0200N100 MOSFET N-Channel Power Trench fig 3ON Semiconductor FDBL0200N100 MOSFET N-Channel Power Trench fig 2ON Semiconductor FDBL0200N100 MOSFET N-Channel Power Trench fig 4

LAND PATTERN RECOMMENDATION
*FOR ADDITIONAL INFORMATION ON OUR PB-FREE STRATEGY AND SOLDERING DETAILS, PLEASE DOWNLOAD THE ON SEMICONDUCTOR SOLDERING AND MOUNTING TECHNIQUES REFERENCE MANUAL, SOLDERRM/D.
NOTES:
1. PACKAGE STANDARD REFERENCE: JEDEC MO-299, ISSUE A.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 2009.
3. CONTROLLING DIMENSION: MILLIMETERS.
4 COPLANARITY APPLIES TO THE EXPOSED WELL AS THE TERMINALS.
5. DIMENSIONS D1 AND El DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. “Al” IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.

DIMMILLIMETERS
MIN.NOM.MAX.
A2.202.302.40
Al1.701.801.90
b0.700.800.90
bl8.00 REF
c0.400.500.60
cl0.10
D9.709.809.90
D19.809.9010.00
D24.73 BSC
D30.40 REF
D43.75 BSC
D51.20
D67.407.507.60
D78.30 REF
E12.12.12.
El10.10.10.
E20.600.700.80
E33.30 REF
E42.60
E53.30
DIMMILLI METERS
MIN.I NOM.I MAX.
E6— 0.65 —
E77.15 REF
E87.I 6.65I 6.75
E95.89 BSC
El05.19 BSC
Ell0.10 REF
e1.20 BSC
e/20.60 BSC
el8.40 BSC
K2.3.3.
L1.902.002.10
1.0.500.600.70
z0.35 REF
912°
aaa0.20
bbb0.25
ccc0.20
ddd0.20
eee0.10

*This information is generic. Please refer to the device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ ”, may or may not be present. Some products may not follow the Generic Marking.

GENERIC MARKING DIAGRAM*ON Semiconductor FDBL0200N100 MOSFET N-Channel Power Trench fig 1 A = Assembly Location
Y = Year
WW = Work Week
ZZ = Assembly Lot Code
XXXX = Specific Device Code
*This information is generic. Please refer to
DOCUMENT NUMBER:98AON13813G
DESCRIPTION: H−PSOF8L 11.68×9.80
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
semi and are trademarks of Semiconductor Components Industries, LLC dba on a semi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semi assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com

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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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For additional information, please contact your local Sales Representative

References

Documents / Resouces

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