Fn-link 3161a-sl Wi-fi Single-band User Manual

Fn-Link 3161A-SL Wi-Fi Single-band User Manual

Overview

Introduction

3161A-SL is a highly integrated 2.4 GHz Wi-Fi module that support the IEEE802.11b/g/nbaseband and RF circuit. It supports 20 MHz standard bandwidth and 5 MHz/10MHznarrow bandwidth, and provides a physical layer rate up to 72.2 Mbit/s. Wi-Fi baseband supports the orthogonal frequency division multiplexing (OFDM) technology and is backward compatible with the direct sequence spread spectrum(DSSS) and complementary code keying (CCK) technologies, offering various data rates defined in the IEEE 802.11 b/g/n protocol.

Module chipset integrates a high-performance 32-bit microprocessor, a hardware security engine, and various peripheral interfaces, including the SPI, UART, I2C, PWM,GPIO, and multi-channel ADC. In addition, it provides high-speed SDIO2.0slave interfaces, with clock frequency up to 50 MHz. Its built-in SRAM and flash can operate independently and even programming is allowed on the flash.

Block Diagram:

Features

• Operate at ISM frequency bands (2.4GHz)
• Maximum rate of 72.2 Mbit/s@HT20 MCS7
• SDIO interface for Wi-Fi
• Low power dissipation
• High transmitting power
• High receiving sensitivity
• PHY supporting IEEE 802.11b/g/n
• MAC supporting IEEE802.11 d/e/h/i/k/v/w
• Module integrated 32K clock
• WFA WPA, WFA WPA2 personal, and WPS2.0 for Wi-Fi
• Built-in 352 KB SRAM and 288 KB ROM
• Main chipset Built-in 32bit MCU and 2 MB flash memory

General Specification

Recommended Operating Rating

Wi-Fi RF Specification

2.4GHz RF Specification

Pin Assignments

Pin Outline

TOP VIEW

Pin Definition

Muti Pin definition

3861L all GPIO pin can configure as muti function,detail see below information.

Notes：

1. IO：Ispu/O.
2. 1mA.
3. 3/1.8V.

Dimensions

Module Picture

L x W : 12 x 12 (+0.3/-0.1) mm

H: 2.3 (±0.2) mm

Weigh:  0.66g

Marking Description

TOP VIEW

Module Physical Dimensions

Unit: mm

TOP VIEW

Layout Recommendation

(Unit: mm)

TOP VIEW

Host Interface Timing Diagram

SDIO Pin Description

The secure digital input/output (SDIO) interface supports three working modes:

Default speed mode (DS)
The maximum frequency of the interface clock is 25 MHz. The interface clock can work in 1-bit or 4-bit mode. High speed mode (HS)
The maximum frequency of the interface clock is 50 MHz. SDR25 mode
The maximum frequency of the interface clock is 50 MHz

SDIO Pin Description 

SD 4-Bit Mode 

DATA0 Data Line 0
DATA1 Data Line 1
DATA2 Data Line 2
DATA3 Data Line 3
CLK Clock
CMD Command Line

SDIO CLK Timing Diagram

DS Mode
The DS mode is the default mode after the SDIO is powered on. To ensure compatibility with various host components, the DS mode requires a low working rate and supports only the 25MHz clock.

Clock parameters in DS mode (VDDIO=3.3 V)

Clock parameters in DS mode (VDDIO= 1.8 V)

Figure 8-6 shows the output data timing in DS mode. tISU is the setup time, that is, the stability time required by the data of the SDIO interface before clock sampling in this mode. tIH is the hold time, that is, the time required by the data of the SDIO interface to retain the original level after clock sampling in this mode.

Figure 8-7 shows the input data timing in DS mode. Where, tODLY(max) is the maximum delay of the output data relative to the clock falling edge, and tODLY(min) is the minimum delay of the output data relative to the clock falling edge.

Table 8-12 describes the timing restrictions in DS mode.

Note: In DS mode, the output data is referenced to the clock falling edge, and the input data is referenced to the clock rising edge.

HS Mode
The HS mode is entered after the SDIO is powered on and initialized because a higher working rate than the DS mode is required. In HS mode, the clock supports 50 MHz. For details about the restrictions on the clock, see Table 8-13.

Table 8-13 Clock perimeters in HS ,ode (VDDIO = 3.3 V)

Table 8-14 Clock perimeters in HS mode (VDDIO = 1.8 V)

Figure 8-8 shows the input data timing in HS mode. tISU is the setup time, that is, the stability time required by the data of the SDIO interface before clock sampling in this mode. tIH is the hold time, that is, the time required by the data of the SDIO interface to retain the original level after clock sampling in this mode.

Figure 8-9 shows the input data timing in HS mode. Where, tODLY(max) is the maximum delay of the output data relative to the clock rising edge, and tOH is the minimum delay of the output data relative to the clock rising edge.

Table 8-15 describes the timing restrictions in HS mode. 

Table 8-15 Timing restrictions in HS mode (VDDIO = 3.3 V)

Table 8-16 Timing restrictions in HS mode (VDDIO = 1.8 V)

Note: The data signal timing in HS mode is different from that in DS mode. The output data and input data are referenced to the clock rising edge.

SDR25 Mode
The SDR25 mode is entered only after the voltage of the SDIO is switched. In this mode, the maximum interface clock frequency is 50 MHz. Table 8-17 describes the clock restrictions.

Table 8-17 Clock perameters in SRD25 fnode (VDDIO =3.3 V)

Table 8-18 Clock Perameters in SDR25 mode (VDDIO = 1.8 V)

Table 8-19 Timing restrictions in SDR25 mode (VDDIO = 3.3 V)

Table 8-19 Timing restrictions in SDR25 mode (VDDIO = 1.8 V)

Reference Design

4line SDIO Reference Design

Notes

1. 4line WLAN module application, all wake function may not supported;
2. Can using Power EN pin to shut down module for power saving;

1line SDIO Reference Design

1. Hi3861L
   GPIO8
   GPIO11
   GPIO12
   GPIO13
2. 3161A WIFI
3. UART  GPIO3/GPIO4
4. GPIO3/GPIO5/GPIO7/GPIO14
5. GPIO7
6. WIFI IO

Ordering Information

The Key Material List

Power on Sequence

VCC / VDDIO supreme electrical order requirements
In the process of power up, GPIO02 internal weak pull low ,the 40MHz crystal is selected..

Design Attention

1. GPIO02 is the interrupt signal of SDIO, It also can be configured as dev wake host function.
2. GPIO8 can be setting as SDIO interrupt function.
3. PMU_PWRON is enable pin of the module. Default is pull high.
4. Wake function may not supported with recently applications, for power saving please using POWER EN pin enable or disable the module.

Recommended Reflow Profile

Referred to IPC/JEDEC standard.
Peak Temperature : <250°C

Number of Times : 2 times 

Packing Information

Reel

A roll of 1500pcs

Carrier Tape Detail

Packaging Detail

Moisture sensitivity

The Modules is a Moisture Sensitive Device level 3, in according with standard IPC/JEDEC J-STD-020, take care all the relatives requirements for using this kind of components. Moreover, the customer has to take care of the following conditions:

a) Calculated shelf life in sealed bag: 12 months at <40°C and <90%relativehumidity(RH). b) Environmental condition during the production: 30°C / 60%RH accordingto IPC/JEDEC J-STD-033A paragraph 5. c) The maximum time between the opening of the sealed bag and the reflow process must be 168 hours if condition
b) “IPC/JEDEC J-STD-033A paragraph 5.2” is respected
d) Baking is required if conditions b) or c) are not respected
e) Baking is required if the humidity indicator inside the bag indicates 10%RHor more.

Customer Service

Office: 6 Floor, Building U6, Junxiang U8 Park, Hangcheng Avenue, Bao’an District, Shenzhen City, CHINA

Factory: No.8, Litong Road, Liuyang Economic & Technical
Development Zone, Changsha, Hunan, CHINA
TEL: +86-755-2955-8186
Website: www.fn-link.com

Customer Approval :
Company
Title
Signature
Date
Fn-Link

References

• Wi-Fi Module, BT Module, IoT Module Manufacturer & Supplier - Fn-Link