Fibocom Fg360-na 5g Wireless Modules User Guide

FG360-NA 5G Wireless Modules

FG360-NA Hardware Guide

Version: Draft V1.0.0

Date: 2022-9-28

Applicability Type: NO. Product Model

Description: This document provides information
on the electrical characteristics, RF performance, dimensions, and
application environment of FG360-NA (hereinafter referred to as
FG360) module. It serves as a guide for developers to understand
the hardware functions of FG360 modules and develop products.

Copyright Notice: Reproduction forbidden
without Fibocom Wireless Inc. written authorization – All rights
reserved.

Overview

Introduction: The FG360-NA module is a hardware
device with several key features that make it an ideal solution for
various applications.

• Key Features:
  • Electrical Characteristics
  • RF Performance
  • Dimensions
  • Application Environment
• Application Framework: This section provides
  an overview of the application framework used in the FG360-NA
  module.
• Antenna Configuration: This section provides
  information on the antenna configuration used in the FG360-NA
  module.
• Warning:
  • Important Notice to OEM integrators: This
    section provides important information to OEM integrators who are
    using the FG360-NA module in their products.
  • FCC Statement: This section provides
    information on FCC regulations and compliance for the FG360-NA
    module.

Pin Definition

Pin Map: This section provides a pin map for
the FG360-NA module.

Table of Pin No. and Pin Name: This section
provides a table of pin numbers and names for the FG360-NA
module.

Pin Definition: This section provides a
detailed pin definition for the FG360-NA module.

Structural Specification

This section provides information on the structural
specification of the FG360-NA module.

Usage Instructions

To use the FG360-NA module, developers should refer to this
hardware guide and other instructions provided by Fibocom Wireless
Inc. They should also ensure compliance with FCC regulations and
follow the pin definition provided in this guide.

Developers should also be aware of the important notice to OEM
integrators provided in this guide and follow the antenna
configuration guidelines.

FG360-NA Hardware Guide
Version: Draft V1.0.0 Date: 2022-9-28

Applicability Type
NO. Product Model

Description

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Copyright
Copyright © 2021 Fibocom Wireless Inc. All rights reserved. Without the prior written permission of the copyright holder, any company or individual is prohibited to excerpt, copy any part of or the entire document, or distribute the document in any form.

Notice
The document is subject to update from time to time owing to the product version upgrade or other reasons. Unless otherwise specified, the document only serves as the user guide. All the statements, information and suggestions contained in the document do not constitute any explicit or implicit guarantee.

Trademark

The trademark is registered and owned by Fibocom Wireless Inc.

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Change History

Version

Author

V1.0.0

Update Date 2022-0-28

Remark Initial version

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Contents
1 Foreword …………………………………………………………………………………………………………6
1.1 Introduction……………………………………………………………………………………………………… 6
2 Overview …………………………………………………………………………………………………………6
2.1 Introduction……………………………………………………………………………………………………… 6 2.1.1 Key Features …………………………………………………………………………………………………..6
2.2 Application Framework ……………………………………………………………………………………… 8 2.3 Antenna Configuration………………………………………………………………………………………. 9 2.4 Waring ……………………………………………………………………………………………………………. 9
2.4.1 Important Notice to OEM integrators …………………………………………………………………..9 2.4.2 FCC Statement ………………………………………………………………………………………………10
3 Pin Definition …………………………………………………………………………………………………12
3.1 Pin Map ………………………………………………………………………………………………………… 12 3.1.1 Table of Pin No. and Pin Name…………………………………………………………………………13 3.1.2 Pin Definition………………………………………………………………………………………………….15
4 Structural Specification ………………………………………………………………………………….23
4.1 Product Appearance……………………………………………………………………………………….. 23 4.2 Dimension of Structure ……………………………………………………………………………………. 23 4.3 Storage…………………………………………………………………………………………………………. 24 4.4 Packing…………………………………………………………………………………………………………. 24

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1 Foreword
1.1 Introduction
The document describes the electrical characteristics, RF performance, dimensions and application environment, etc. of FG360-NA (hereinafter referred to as FG360). With the assistance of the document and other instructions, the developers can quickly understand the hardware functions of FG360 modules and develop products.
2 Overview
2.1 Introduction
The FG360 series module is a 5G module which supports NSA and SA network architectures. The FG360 integrates core devices such as Baseband, Memory, PMU, Transceiver, and PA. It supports 5G NR Sub6, FDD-LTE, and TDD-LTE long-distance communication modes. Supports uplink 2×2 MIMO and downlink 4×4 MIMO multi-antenna configuration in SA mode. It also supports GNSS wireless positioning technology. The FG360 is designed in an LGA package and is suitable for a variety of eMBB scenarios, such as CPE, VR/AR, gateway, TV box, and intelligent monitoring.

2.1.1Key Features

Table 2-1 Key features

Performance

Description

LTE FDD: B2, B4, B5, B12, B25, B48, B66, B71

Operating Band

LTE TDD: B41, B48

NR: n25, n41, n48, n66, n71, n77

GNSS

Support GPS, GLONASS, Galileo, BDS, QZSS

NR

3GPP Release 15

LTE Feature

3GPP Release 15
NR: DL 4×4 MIMO: n25, n41, n48, n66, n71, n77 UL 2×2MIMO: n41, n77
LTE: DL 4×4MIMO: B2, B4, B25, B41, B48, B66, B71

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Data Transmission
Power Supply
Temperature
Physical characteristics CPU Memory

NSA and SA supported

SRS: n41, n77 Support: 1T2R, 1T4R, 2T4R

HPUE: B41, n41, n77

SA 5G/NR Sub-6 Peak DL 4.43Gbps/UL 1.25Gbps

NSA Peak

DL 3.74Gbps/UL 700Mbps

LTE

DL 1.6Gbps (CAT19)/UL 211Mbps (CAT18)

DC: 3.3~4.4V, typical voltage: 3.8V Normal operating temperature: -30~751 Extended operating temperature: -40~852
Storage temperature: -40~85 Dimension: 41 mm×44mm×2.75 mm Package: 430 pin LGA Weight: about 12.0 g
ARM Cortex-A55, quad core, up to 2.0 GHz

2GB LPDDR4x+32GB eMMC Flash

Interface USB Interface PCIe Interface
SIM Interface
I2C ADCs

USB2.0 high speed (HS) interface, data transmission rate up to 480Mbps USB3.0 Super-speed (SS) interface, data transmission rate up to 5Gbps
PCIe Gen3 2Lane×1, PCIe Gen3 1Lane×2 (PCIe only support RC mode) Dual SIM: 1.8V/3V SIM1: USIM SIM2: ESIM/USIM
One set of I2C interface, data transmission rate up to 400Kbit/s
A/D conversion channel, Voltage Range: 0~1.45V

Software Firmware update

USB/PCIe/FOTA

Operating System Linux/Android/Windows

Note 1. When temperature keeps in the range of -30~75°C, the module can work normally. Module
performance meets the 3GPP specifications. 2. When temperature keeps in the range of -40~85°C, module performance may be slightly out of
3GPP specifications.

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2.2 Application Framework

The application framework below shows the main hardware functions of the FG360 module: Baseband RF transceiver PMU Memory Peripheral interface

ANT0

ANT1

ANT2 ANT3 ANT4 ANT5

GNSS

VBAT
PWRKEY RESET_N

ET

TRX Blocks

Main PMU

RFCLK 26MHz

TX

RX

RFFE

Transceiver

eMCP

LPDDR4X

eMMC

Sub PMU

26MHz Crystal

SPMI Sleep CLK
32KHz

BBCLK 26MHz

RFFE

DRF
Baseband

USIM1

eSIM

JTAG

GPIO/EINT

Coex UART

SDIO SGMII

SPI

DSI I2C I2S PCIe3.0 USB2.0/3.0 UART ADCs MIPI

Figure 2-1 Hardware block diagram

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2.3 Antenna Configuration

FG360 module supports seven antennas and the configuration is as below table:

PAD Function

Band Configuration(TX) Band

Description

130

LB TRX MHB sec TRX

B2/4/5/12/25/41/48/66/71 n25/41/48/66/71/77

Configuration(RX) B2/4/5/12/25/41/48/66/71
n25/41/48/66/71/77

175

MHB TRX

B2/4/25/41/48/66

LB RX

n25/41/48/66/77

B2/4/25/41/48/66/71 n25/41/48/66/71/77

157 LMHB Rx

Only SRS

B2/4/25/66/71

n25/66/71

139 LMHB Rx

Only SRS

B2/4/5/12/66/71

n25/66/71

148 HUB Rx

Only SRS

B41/48

n41/48/77

193 HUB Rx

Only SRS

B41/48

n41/48/77

199 GNSS

GNSS receive

Frequency Range(MHz) 617~4200
617~4200 617~2200
617~2200
2496~4200
2496~4200

2.4 Waring

2.4.1 Important Notice to OEM integrators

1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.31 (h) and (k): The host manufacturer is responsible for additional testing to verify compliance as a composite system. When testing the host device for compliance with Part 15 Subpart B, the host manufacturer is required to show compliance with Part 15 Subpart B while the transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation should confirm that the module’s intentional emissions are compliant (i.e. fundamental and out of band emissions). The host manufacturer must verify that there are no additional unintentional emissions other than what is permitted in Part 15 Subpart B or emissions are complaint with the transmitter(s) rule(s). The Grantee will provide guidance to the host manufacturer for Part 15 B requirements if needed.
Important Note

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notice that any deviation(s) from the defined parameters of the antenna trace, as described by the instructions, require that the host product manufacturer must notify to Fibocom Wireless Inc. that they wish to change the antenna trace design. In this case, a Class II permissive change application is required to be filed by the USI, or the host manufacturer can take responsibility through the change in FCC ID (new application) procedure followed by a Class II permissive change application.
End Product Labeling
When the module is installed in the host device, the FCC/IC ID label must be visible through a window on the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a second label must be placed on the outside of the final device that contains the following text: “Contains FCC ID: ZMOFG360NA08” The FCC ID can be used only when all FCC mpliance requirements are met.
Antenna Installation
(1) The antenna must be installed such that 20 cm is maintained between the antenna and users, (2) The transmitter module may not be co-located with any other transmitter or antenna. (3) Only antennas of the same type and with equal or less gains as shown below may be used with this module. Other types of antennas and/or higher gain antennas may require additional authorization for operation. (4)The max allowed antenna gain is 3.76dBi for external monopole antenna.

In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC/IC authorization.

Manual Information to the End User
The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the user’s manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual.

2.4.2 FCC Statement

Federal Communication Commission Interference Statement
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

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(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures: – Reorient or relocate the receiving antenna. – Increase the separation between the equipment and receiver. – Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. – Consult the dealer or an experienced radio/TV technician for help.
Any changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate this equipment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.
This device is intended only for OEM integrators under the following conditions: (For module device use)
1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed.
Radiation Exposure Statement
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator & your body.

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3 Pin Definition
The FG360 module applies LGA interface with 430 pins.
3.1 Pin Map

391

133

136

139

142

145

148

151

154

157

160

163

166

169

172

175

178

181

184

187

190

193

195 194

392

134

137

140

143

146

149

152

155

158

161

164

167

170

173

176

179

182

185

188

191

135

138

141

144

147

150

153

156

159

162

165

168

171

174

177

180

183

186

189

192

196

197

199

198

200

202

201

203

412

205

204

206

413

208

207

209

414

211

210

212

415

214

213

215

416

217

216

218

417

220

219

221

418

223

222

224

419

226

225

227

420

229

228

230

421

232

231

233

422

235

234

236

423

238

237

239

424

241

240

242

425

244

243

245

426

247

246

248

427

250

249

251

428

253

252

254

429

256

255

257

430

259

258

260

262

261

263

264

298

132

131

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

129

130

128

126

127

411

125

123

124

299

300

301

302

303

304

305

306

307

410

122

120

121

409

119

117

118

308

309

310

311

312

313

314

315

316

408

116

114

115

317

318

319

320

321

322

323

324

325

407

113

111

112

406

110

108

109

326

327

328

329

330

331

332

333

334

405

107

105

106

404

104

102

103

335

336

337

338

339

340

341

342

343

403

101

99

100

344

345

346

347

348

349

350

351

352

402

98

96

97

401

95

93

94

353

354

355

356

357

358

359

360

361

400

92

90

91

399

89

87

88

362

363

364

365

366

367

368

369

370

398

86

84

85

397

83

81

82

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

396

80

78

79

395

77

75

76

394

74

72

73

393

71

69

70

68

66

67

281

280

279

278

277

276

275

274

273

272

271

270

269

268

267

266

65

64

265 9

60

57

54

51

48

45

42

39

36

33

30

27

24

21

18

15

12

6

3

62 63

59

56

53

50

47

44

41

38

35

32

29

26

23

20

17

14

11

8 10

5

2

390

61

58

55

52

49

46

43

40

37

34

31

28

25

22

19

16

13

389

7

4

1

Power Pins PCIe Pins ADC Pins CTL Pins

GND Pins LCD Pins UART Pins SGMII Pins

GPIO Pins (U)SIM Pins SPI Pins GRFC&RFFE

RESERVED/NC Pins USB Pins ANT Pins I2S Pins

Figure 3-1 Pin map

I2C Pins BT&WIFI Pins SDIO Pins CLOCK Pins

Note The pin “RESERVED” means that the position pin is reserved and does not need to be connected.

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3.1.1 Table of Pin No. and Pin Name

Table 3-1 Table of pin no. and pin name

No.

PIN Name

No.

PIN Name

No.

PIN Name

No.

1

PWRKEY

2

PON_1

3

CLK_OUT

4

6

SPI0_CSB

7

SIM1_VDD

8

SPI0_MOSI

9

11

SIM2_RST

12

SIM2_DATA

13

SIM1_CLK

14

16

SIM1_RST

17

SGMII_1_TXN

18

SIM2_VDD

19

21

SGMII_0_TXP

22

SGMII_1_RXN

23

RESERVED

24

26

PCIE_B_LN0_TXN 27

EINT17

28

GBE0_RST

29

31

GND

32

RESERVED

33

PCIE_B_LN0_RXN 34

37

PCIE_A_CLKP

38

PCIE_D_LN0_TXP 39

PCIE_D_LN0_TXN 40

42

GND

43

PCIE_A_LN0_TXP 44

PCIE_D_LN0_RXN 45

47

SDC_CMD

48

RESERVED

49

PCIE_A_LN0_RXP 50

52

GND

53

SDC_DATA1

54

SDC_DATA3

55

57

VBUS_DET

58

SSUSB_TXP

59

USB_DM

60

62

USB_DP

63

SSUSB_RXP

64

AP_URTS1

65

67

PCIE_B_PEWAKEN 68

G3BE1_RST

69

MDIO

70

72

LSDA

73

AP_URXD1

74

LSDI

75

77 84~89 96 101

AP_UTXD1 VBAT_RF PCM0_CLK I2S0_BCK

78 90~92 97 102

LRSTB GND PCM0_DO PTA_RX

79

AP_UCTS1

80

93

PCM0_SYNC

94

98

CDC_RESET_N 99

103

I2S0_DO

104

106

NET_STATUS

107

AUDIO_PWR_EN 108

STATUS

109

111

SLEEP_IND

112

I2C_SCL0

116

ANTCTL3

117

IRIG_B

122

GND

123

EINT20

129

DBG_UART_TX 130

ANT8_M

113

WAKEUP_IN

114

118~119 GND

120

124~125 GND

126

131~134 GND

135

138

BT_URXD

139

ANT7_D

140

GND

141

144

EINT16

145~147 GND

148

ANT6

149

151~152 GND

153

BT_ACT_TXD

154~155 GND

156

158

GND

159

USB_DRVBUS

160~161 GND

162

PIN Name

No.

PIN Name

SYS_RESIN_N

5

SPI0_MISO

SPI0_CLK

10

SIM1_DATA

SIM1_DET

15

SIM2_CLK

GND

20

SGMII_1_TXP

SGMII_0_TXN

25

SGMII_1_RXP

PCIE_B_LN0_TXP 30

PCIE_B_LN0_RXP

PCIE_A_CLKN

35~36

GND

PCIE_A_LN0_TXN 41

PCIE_D_LN0_RXP

SDC_CLK

46

PCIE_A_LN0_RXN

GND

51

SDC_DATA2

SSUSB_TXN

56

SDC_DATA0

USB_ID

61

SSUSB_RXN

GBE1_INT

66

MDC

PCIE_B_CLKREQN 71

LSCE0B

LSA0

76

PCIE_B_PERSTN

LSCK

81~83

GND

I2S0_MCK

95

PCM0_DI

PTA_TX

100

CDC_INT1_N

I2S0_DI

105

I2S0_LRCK

W_DISABLE

110

NET_MODE

ISINK1

115

I2C_SDA0

GPS_PPS

121

NC

DBG_UART_RX 127~128 GND

BT_UTXD

136~137 GND

DSI_TE

142~143 GND

GND

150

BT_PRI_RXD

DISP_PWM

157

ANT5_M2

GPIO78/ 163~164
PCIE_D_CLKREQN

GND

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No.

PIN Name

No.

PIN Name

No.

PIN Name

No.

PIN Name

No.

PIN Name

165

NC

166

NC

167

GND

168

NC

169~170 GND

171

NC

172~173 GND

174

NC

175

ANT3_M1

176

GND

177

NC

178~179 GND

180

LCD_PWR_EN2 181~182 GND

183

TDI

184

NC

185

GND

186

TCK

187~188 GND

189

TDO

190~192 GND

193

ANT1

194~197 GND

198

MIPI1_D_SDATA 199

ANT10_GNSS

200

GND

201

MIPI1_D_SCLK

202~203 GND

204

ANTCTL2

205

NC

206

GND

207

ANTCTL1

208

GND

GPIO76/

209

210

ANTCTL0

PCIE_D_PERSTN

211

SDIO_VDD

212

EINT15

213~215 GND

216

MIPI2_D_SDATA 217

RESERVED

218

GND

219

MIPI2_D_SCLK

220~222 GND

223

RESERVED

224

GND

225

VDD_EXT_1V8

226~228 GND

229

RESERVED

230

GND

231

NC

232~234 GND

235

RESERVED

236

GND

237

RESERVED

238~239 GND

240~241 RESERVED

242

GND

243

RESERVED

244~245 GND

246~247 RESERVED

248

GND

249

ADC0

250~251 GND

252

ADC1

253

RESERVED

254

GND

255

NC

256~258 GND

259

RESERVED

260

GND

261

VBAT_BB

262

GND

263~264 VBAT_BB

265

PCIE_D_CLKN

266

GND

267

SIM2_DET

268

SGMII_0_RXP

269

SGMII_0_RXN

270

SGMII_PWR_EN1 271

PCIE_B_CLKP

272

PCIE_B_CLKN

273

USB_BOOT

274

PCIE_A_PEWAKEN 275

PCIE_A_PERSTN 276

PCIE_A_CLKREQN

277

GND

278

GBE0_INT

279

EINT18

280

SDC_DET

281

SD_PWR_EN

282

BT_URTS

283

BT_UCTS

284

GND

GPIO77/

285

286

WIFI_GPIO1

PCIE_D_PEWAKEN

287

WLAN_ACT

288

LCM_RST

289

GND

290

NC

291

WIFI_GPIO2

292

NC

293

RESERVED

294

NC

295

TRST_N

296

TMS

297

SYSRSTB

298

LCD_PWR_EN1 299~392 GND

393

PCIE_C_LN0_RXN 394

PCIE_C_LN0_RXP

395

PCIE_C_LN0_TXP 396

PCIE_C_LN0_TXN 397~398 GND

399

PCIE_C_CLKP

400

PCIE_C_CLKN

401

PCIE_C_PERSTN 402

PCIE_C_CLKREQN 403

PCIE_C_PEWAKEN 404

DSI0_D0P

405

DSI0_D0N

406

DSI0_CKN

407

DSI0_CKP

408

DSI0_D1N

409

DSI0_D1P

410~425 NC

426

RESERVED

427

RESERVED

428

RESERVED

429

RESERVED

430

RESERVED

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3.1.2 Pin Definition
Table 3-2 IO Parameter definition Type PI PO DI DO DIO AI AO AIO OD PU PD Hi-Z

Description Power Input Power Output Digital Input Digital Output Digital Input/Output Analog Input Analog Output Analog Input/Output Open Drain Internal pull up Internal pull down High impedance

Table 3-3 LGA pin description

Pin Name Power VBAT_BB
VBAT_RF
VDD_EXT_1V8 USB

Pin No.

Type

261 263, 264 PI

84, 85, 86, 87, PI 88, 89

225

PO

SSUSB_TXN

55

AO

SSUSB_TXP

58

AO

SSUSB_RXN

61

AI

SSUSB_RXP

63

AI

USB_DM

59

AIO

USB_DP

62

AIO

VBUS_DET

57

DI

USB_DRVBUS

159

DO

USB_ID

60

DI

USIM

Power Domain Reset Value Pin Description

–

–

Baseband power input

–

–

RF power input

–

–

1.8V power output

–

–

–

–

–

–

–

–

–

–

–

–

–

–

VDD_EXT_1V8 PD

VDD_EXT_1V8 PD

USB super speed transmit data minus USB super speed transmit data plus USB super speed receive data minus USB super speed receive data plus USB high speed data minus USB high speed data plus USB VBUS detection USB OTG power enable USB ID

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Pin Name SIM1_VDD SIM1_DATA SIM1_CLK SIM1_RST SIM1_DET
SIM2_VDD

Pin No. 7 10 13 16 14
18

SIM2_DATA

12

SIM2_CLK

15

SIM2_RST

11

SIM2_DET

267

GPIO

W_DISABLE

109

WAKEUP_IN

113

NET_STATUS

106

NET_MODE

110

SLEEP_IND

111

STATUS

108

IRIG_B

117

GPS_PPS

120

ISINK1

114

ANT

ANT1

193

NC

184

ANT3_M1

175

NC

166

ANT5_M2

157

ANT6

148

ANT7_D

139

ANT8_M

130

NC

121

ANT10_GNSS

199

NC

205

ANT Tuner Control

MIPI1_D_SDATA 198

MIPI1_D_SCLK

201

MIPI2_D_SDATA 216

Type PO DIO DO DO DI
PO
DIO
DO DO DI

Power Domain Reset Value Pin Description

–

–

SIM1 power supply,3V/1.8V

SIM1_VDD

PD

SIM1 data input/output

SIM1_VDD

PD

SIM1 clock signal

SIM1_VDD

PD

SIM1 reset signal

VDD_EXT_1V8 PD

SIM1 detect signal

–

–

SIM2 power supply,3V/1.8V, Reserved

SIM2_VDD

PD

SIM2 data input/output, Reserved

SIM2_VDD

PD

SIM2 clock signal, Reserved

SIM2_VDD

PD

SIM2 reset signal, Reserved

VDD_EXT_1V8 PD

SIM2 detect, Reserved

DI VDD_EXT_1V8 PD

DI VDD_EXT_1V8 PD

DO VDD_EXT_1V8 PD

DO VDD_EXT_1V8 PD

DO VDD_EXT_1V8 PD

DO VDD_EXT_1V8 PD

DO VDD_EXT_1V8 PD

DO VDD_EXT_1V8 PD

AI

VBAT_BB

HI-Z

Module airplane mode control signal Module wake up input from host Module network status indication Module network mode indication Module output to wake up host Module current working status indication B code output PPS signal output LED negative drive signal

AIO –

AIO –

AIO –

AIO –

AIO –

AIO –

AIO –

AIO –

AIO –

AI

–

AIO –

–

UCB TRx

–

NC

–

41 TRx + MHB/UCB/LAA Rx

–

NC

–

MHB/UCB/LAA Rx

–

UCB TRx

–

LMHB Rx

–

LMH TRX

–

NC

–

GNSS antenna

–

NC

DIO VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD DIO VDD_EXT_1V8 PD

External Tuner MIPI Control Data Pin External Tuner MIPI Control Clock Pin External Tuner MIPI Control Data Pin

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Pin Name MIPI2_D_SCLK ANTCTL0 ANTCTL1 ANTCTL2 ANTCTL3 Module Control PWRKEY SYS_RESIN_N PON_1
EINT20

Pin No. 219 210 207 204 116
1 4 2
123

USB_BOOT

273

SD

SDC_CMD

47

SDC_DATA1

53

SDC_DATA0

56

SDC_CLK

45

SDC_DATA2

51

SDC_DATA3

54

SDC_DET

280

SD_PWR_EN

281

SDIO_VDD

211

SGMII

SGMII_1_RXN

22

SGMII_1_RXP

25

SGMII_1_TXN

17

SGMII_1_TXP

20

GBE1_INT

65

GBE1_RST

68

SGMII_0_RXN

269

SGMII_0_RXP

268

SGMII_0_TXN

24

SGMII_0_TXP

21

Type
DO
DO DO DO DO

Power Domain
VDD_EXT_1V8
1.8V 1.8V 1.8V 1.8V

Reset Value
PD
PD PD PD PD

Pin Description External Tuner MIPI Control Clock Pin Antenna control signal 0 Antenna control signal 1 Antenna control signal 2 Antenna control signal 3

DI 1.8V

PU

DI 1.8V

PU

DI

VBAT_BB

PU

DI VDD_EXT_1V8 PD

DI VDD_EXT_1V8 PD

Module power-key control signal Module reset control signal
Module power on signal
MT6890 interruput input signal, used for WPS key input signal Force into USB download boot mode

DIO SDIO_VDD

PD

DIO SDIO_VDD

PD

DIO SDIO_VDD

PD

DO SDIO_VDD

PD

DIO SDIO_VDD

PD

DIO SDIO_VDD

PD

DI VDD_EXT_1V8 PD

DO VDD_EXT_1V8 PD

PO –

–

SDC interface command signal SDC interface DATA1 signal SDC interface DATA0 signal SDC interface clock signal SDC interface DATA2 signal SDC interface DATA3 signal SD card insert detection SD card power supply enable SDC interface I/O power domain

AIO AVDD12_SGMI I

AIO AVDD12_SGMI I

AIO AVDD12_SGMI I

AIO AVDD12_SGMI I

DI VDD_EXT_1V8 PD

DO VDD_EXT_1V8 PD

AIO

AVDD12_SGMI I

–

AIO

AVDD12_SGMI I

–

AIO

AVDD12_SGMI I

–

AVDD12_SGMI

AIO I

–

SGMII 1 receive data minus SGMII 1 receive data plus SGMII 1 transmit data minus SGMII 1 transmit data plus SGMII 1 interrupt input signal SGMII 1 reset signal SGMII 0 receive data minus SGMII 0 receive data plus SGMII 0 transmit data minus SGMII 0 transmit data plus

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Pin Name

Pin No.

GBE0_INT

278

GBE0_RST

28

SGMII_PWR_EN1 270

MDIO

69

MDC

66

PCIE

PCIE_A_CLKN

34

PCIE_A_CLKP

37

PCIE_A_LN0_TXN 40

PCIE_A_LN0_TXP 43

PCIE_A_LN0_RXN 46

PCIE_A_LN0_RXP 49

PCIE_A_PEWAKEN 274

PCIE_A_PERSTN 275

PCIE_A_CLKREQN 276

PCIE_B_CLKN

272

PCIE_B_CLKP

271

PCIE_B_LN0_TXN 26

PCIE_B_LN0_TXP 29

PCIE_B_LN0_RXN 33

PCIE_B_LN0_RXP 30

PCIE_B_PEWAKEN 67

PCIE_B_PERSTN 76

PCIE_B_CLKREQN 70

PCIE_C_CLKN

400

PCIE_C_CLKP

399

PCIE_C_LN0_TXN 396

PCIE_C_LN0_TXP 395

PCIE_C_LN0_RXN 393

PCIE_C_LN0_RXP 394

PCIE_C_PEWAKEN 403

PCIE_C_PERSTN 401

PCIE_C_CLKREQN 402

PCIE_D_CLKN

3

PCIE_D_CLKP

265

PCIE_D_LN0_TXN 39 PCIE_D_LN0_TXP 38 PCIE_D_LN0_RXN 44 PCIE_D_LN0_RXP 41

GPIO76/ PCIE_D_PERSTN

209

GPIO77/

285

PCIE_D_PEWAKEN

Type DI DO DO DIO DO

Power Domain VDD_EXT_1V8 VDD_EXT_1V8 VDD_EXT_1V8 VDD_EXT_1V8 VDD_EXT_1V8

Reset Value PD PD PD PD PD

Pin Description SGMII 0 interrupt input signal SGMII 0 reset signal SGMII power supply enable 1 SGMII MDIO signal SGMII MDC signal

AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE DI VDD_EXT_1V8 PU DO VDD_EXT_1V8 PU DIO VDD_EXT_1V8 PU AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE DI VDD_EXT_1V8 PU DO VDD_EXT_1V8 PU DIO VDD_EXT_1V8 PU AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE DI VDD_EXT_1V8 PU DO VDD_EXT_1V8 PU DIO VDD_EXT_1V8 PU
AIO AVDD12_PCIE –
AIO AVDD12_PCIE –
AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE AIO AVDD12_PCIE –
DI VDD_EXT_1V8 PD
DO VDD_EXT_1V8 PD

PCIe A reference clock minus PCIe A reference clock plus PCIe A Tx0 minus PCIe A Tx0 plus PCIe A Rx0 minus PCIe A Rx0 plus PCIe A wake-up signal PCIe A reset signal PCIe A clock request signal PCIe B reference clock minus PCIe B reference clock plus PCIe B Tx0 minus PCIe B Tx0 plus PCIe B Rx0 minus PCIe B Rx0 plus PCIe B wake-up signal PCIe B reset signal PCIe B clock request signal PCIe C reference clock minus PCIe C reference clock plus PCIe C Tx0 minus PCIe CTx0 plus PCIe C Rx0 minus PCIe C Rx0 plus PCIe C wake-up signal PCIe C reset signal PCIe C clock request signal PCIe D reference clock minus, Reserved PCIe D reference clock plus, Reserved PCIe D Tx0 minus, Reserved PCIe D Tx0 plus, Reserved PCIe D Rx0 minus, Reserved PCIe D Rx0 plus, Reserved MT6890 GPIO, used for 2+2+4 and 4+4+4 WIFI/BT and RF co-exist control signals MT6890 GPIO, used for 2+2+4 and 4+4+4 WIFI/BT

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Pin Name

Pin No.

GPIO78/ PCIE_D_CLKREQN

162

JTAG

TDI

183

TCK

186

TDO

189

TRST_N

295

TMS

296

SYSRSTB

297

I2C

I2C_SDA0

115

I2C_SCL0

112

I2S

I2S0_DO

103

I2S0_MCK

94

I2S0_DI

104

I2S0_BCK

101

I2S0_LRCK

105

ADC

ADC0

249

ADC1

252

Debug UART

DBG_UART_TX

129

DBG_UART_RX 126

UART

AP_UCTS1

79

AP_URTS1

64

AP_UTXD1

77

AP_URXD1

73

SPI

SPI0_MISO

5

SPI0_MOSI

8

SPI0_CSB

6

SPI0_CLK

9

AUDIO CODEC

CDC_RESET_N

98

CDC_INT1_N

100

Type DO

Power Domain VDD_EXT_1V8

Reset Value PD

Pin Description and RF co-exist control signals MT6890 GPIO, used for 2+2+4 and 4+4+4 WIFI/BT and RF co-exist control signals

DI VDD_EXT_1V8 PD DI VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD DI VDD_EXT_1V8 PD DI VDD_EXT_1V8 PD DI VDD_EXT_1V8 PD

JTAG TDIReserved JTAG TCKReserved JTAG TDOReserved JTAG TRSTReserved JTAG TMSReserved System resetReserved

DIO VDD_EXT_1V8 PU DO VDD_EXT_1V8 PU

DO VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD DI VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD

AI

VDD_EXT_1V8 –

AI

VDD_EXT_1V8 –

DO VDD_EXT_1V8 PU DI VDD_EXT_1V8 PU
DI VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD DI VDD_EXT_1V8 PD
DI VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD
DO VDD_EXT_1V8 PD DI VDD_EXT_1V8 PD

I2C data I2C clock
I2S data output signal I2S clock output signal I2S data input signal I2S data bit clock signal I2S frame clock signal
A/D conversion channel 0 A/D conversion channel 1
Debug UART data transmission Debug UART data reception
UART receive ready signal UART transmit request signal UART transmit signal UART receive signal
SPI interface input signal SPI interface output signal SPI interface chip select signal SPI interface clock signal
External CODEC reset signal External CODEC interrupt signal

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Pin Name AUDIO_PWR_EN LCD

Pin No. 107

LSCK

80

LSDA

72

LSA0

75

LSCE0B

71

LSDI

74

LRSTB

78

DSI_TE

141

DISP_PWM

156

LCM_RST

288

LCD_PWR_EN1 298

LCD_PWR_EN2 180

DSI0_CKN

406

DSI0_CKP

407

DSI0_D0N

405

DSI0_D0P

404

DSI0_D1N

408

DSI0_D1P

409

WIFI/BT

BT_UTXD

135

BT_URXD

138

Type DO

Power Domain Reset Value Pin Description

VDD_EXT_1V8 PD

External CODEC power enable

DO VDD_EXT_1V8 PD
DO/DI VDD_EXT_1V8 PD
DO VDD_EXT_1V8 PD
DO VDD_EXT_1V8 PD
DI VDD_EXT_1V8 PD
DO VDD_EXT_1V8 PD DI VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD DO VDD_EXT_1V8 PD AIO AVDD12_DSI AIO AVDD12_DSI AIO AVDD12_DSI AIO AVDD12_DSI AIO AVDD12_DSI AIO AVDD12_DSI –

CLK signal for DBI-C serial 3/4 wire SPI LCD, connect to LCD CLK signal Data signal for DBI-C serial 3/4 wire SPI LCD. For type interface I LCD, is data input/output signal. For type interface II LCD, is data output signal from FG360 module and connect to LCD data in signal RS signal for DBI-C serial 4 wire SPI LCD, DBI-C serial 3 wire SPI LCD not has this signal CS signal for DBI-C serial 3/4 wire SPI LCD, connect to LCD CS signal Data signal for DBI-C serial 3/4 wire SPI LCD. For type interface II LCD, is data input signal from FG360 module and connect to LCD data output signal. For type interface I LCD, not has this signal Reset signal for DBI-C serial 3/4 wire SPI LCD, connect to LCD RST signal LCD frame synchronization signal LCD Backlight control PWM signal DSI LCD reset signal LCD power supply enable 1 LCD power supply enable 2 DSI LCD MIPI CLK minus DSI LCD MIPI CLK plus DSI LCD MIPI lane0 minus DSI LCD MIPI lane0 plus DSI LCD MIPI lane1 minus DSI LCD MIPI lane1 plus

DO VDD_EXT_1V8 PD DI VDD_EXT_1V8 PD

UART TX signal UART RX signal

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Pin Name BT_URTS BT_UCTS PCM0_DO PCM0_DI PCM0_CLK PCM0_SYNC
EINT16
EINT17
EINT18
EINT15
BT_PRI_RXD
BT_ACT_TXD
WLAN_ACT
PTA_TX
PTA_RX
WIFI_GPIO1
WIFI_GPIO2 MMW NC NC NC NC NC NC NC NC NC NC NC NC Reserved RESERVED NC

Pin No. 282 283 97 95 96 93 144
27
279
212 150 153 287 99 102 286 291

Type DO DI DO DI DO DO DO
DO
DO
DI DI DO DI DO DI DIO DIO

Power Domain Reset Value Pin Description

VDD_EXT_1V8 PD

UART RTS signal

VDD_EXT_1V8 PD

UART CTS signal

VDD_EXT_1V8 PD

PCM data output

VDD_EXT_1V8 PD

PCM data input

VDD_EXT_1V8 PD

PCM clock output

VDD_EXT_1V8 PD

PCM synchronization signal

MT6890 GPIO, used for

VDD_EXT_1V8 PD

control WIFI RESET signal or

WIFI Power enable signal

MT6890 GPIO, used for

VDD_EXT_1V8 PD

control WIFI RESET signal or

WIFI Power enable signal

MT6890 GPIO, used for

VDD_EXT_1V8 PD

control WIFI RESET signal or

WIFI Power enable signal

VDD_EXT_1V8 PD

Interrupt input signal, used as WLAN_EN

VDD_EXT_1V8 PD

WIFI/BT and RF co-exist control signals

VDD_EXT_1V8 PD

WIFI/BT and RF co-exist control signals

VDD_EXT_1V8 PD

WIFI/BT and RF co-exist control signals

VDD_EXT_1V8 PD

WIFI/BT and RF co-exist control signals

VDD_EXT_1V8 PD

WIFI/BT and RF co-exist control signals

VDD_EXT_1V8 PD

WIFI control signal 1, Reserved

VDD_EXT_1V8 PD

WIFI control signal 2, Reserved

237

–

–

223

–

–

217

–

–

240

–

–

235

–

–

229

–

–

243

–

–

247

–

–

241

–

–

246

–

–

259

–

–

253

–

–

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

23, 32, 48,

–

–

293,426~430

–

–

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Pin Name NC

Pin No. 165,168,171, 174,177,231, 255,290,292, 294,410~425

Type –

Power Domain Reset Value Pin Description

–

–

–

Pin Name GND
GND

Pin No.
19, 31, 35, 36, 42, 50, 52, 81, 82, 83, 90, 91, 92, 118, 119, 122, 124, 125, 127, 128, 131, 132, 133, 134, 136, 137, 140, 142, 143, 145, 146, 147, 149, 151, 152, 154, 155, 158, 160, 161, 163, 164, 167, 169, 170, 172, 173, 176, 178, 179, 181, 182, 185, 187, 188, 190, 191, 192, 194, 195, 196, 197, 200, 202, 203, 206, 208, 213, 214, 215, 218, 220, 221, 222, 224, 226, 227, 228, 230, 232, 233, 234, 236, 238, 239, 242, 244, 245, 248, 250, 251, 254, 256, 257, 258, 260, 262, 266, 277, 284, 289, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 397,398

Note 1. The PWRKEY and SYS_RESIN_N pins have internal pull-up, and the pull-up power supply is in
exclusive mode; no external pull-up is required; PON_1 pin module with weak pull-down, maximum input voltage must not exceed VBAT_BB.

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4 Structural Specification
4.1 Product Appearance
The appearance of the FG360 module product is as shown:
Figure 4-1 Module product appearance
4.2 Dimension of Structure
The structural dimensions of the FG360 module are shown in the figure:

Figure 4-2 Structure size chart Note Unmarked dimensional tolerances are 0.1mm.

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4.3 Storage
Refer to FIBOCOM FG360-NA Series SMT Design Guide.
4.4 Packing
Refer to FIBOCOM FG360-NA Series SMT Design Guide.

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