LMT035KDH03-NHN LCD Module

LMT035KDH03-NHN LCD Module User Manual

Prepared by: Wangxikuan

Date: 2022-02-15

Checked by: Date:

Approved by: Date:

Table of Content

General Specification
Block Diagram
- Terminal Functions
Absolute Maximum Ratings
Electrical Characteristics
- DC Characteristics
- AC Characteristics
  - 8080 Mode Timing
  - SPI Mode Timing
  - Reset Timing
Optical Characteristics
Function Specifications
- Command Summary
LCD Module Design and Handling Precautions
CTP Mounting Instructions
RTP Mounting Instructions

1. General Specification

Screen Size(Diagonal):
Resolution:
Interface:
Color Depth:
Dot Pitch:
Pixel Configuration:
Display Mode:
Surface Treatment:
Viewing Direction:
Outline Dimension:
Active Area:
Weight:
Backlight:
Operating Temperature:
Storage Temperature:

Note: Backlight color may slightly change over temperature and
driving voltage.

2. Block Diagram

2.1 Terminal Functions

Terminal Functions

Product Usage Instructions

Please refer to the product user manual for detailed information
on the LCD module, including its general specifications, block
diagram, terminal functions, absolute maximum ratings, electrical
characteristics, optical characteristics, function specifications,
LCD module design and handling precautions, and mounting
instructions.

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LMT035KDH03-NHN LCD Module User Manual

Prepared by: Wangxikuan
Date: 2022-02-15

Checked by: Date:

Approved by: Date:

Rev.
0.1 0.2 0.3 0.4

Descriptions
New release Add Terminal description and timing of SPI mode Update Section 2.1 Update Terminal Functions

Release Date
2015-07-22 2015-08-05 2018-03-19 2022-02-15

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Table of Content
1. General Specification ……………………………………………………………………………………………… 3

2. Block Diagram………………………………………………………………………………………………………… 3 2.1 Terminal Functions………………………………………………………………………………………………… 4

3. Absolute Maximum Ratings …………………………………………………………………………………….. 4

4. Electrical Characteristics ………………………………………………………………………………………… 5

4.1 DC Characteristics ………………………………………………………………………………………………… 5

4.2 AC Characteristics…………………………………………………………………………………………………. 5

4.2.1 4.2.2 4.2.3

8080 Mode Timing ……………………………………………………………………………………….. 5 SPI Mode Timing …………………………………………………………………………………………. 6 Reset Timing ………………………………………………………………………………………………. 8

5. Optical Characteristics ……………………………………………………………………………………………. 9

6. Function Specifications…………………………………………………………………………………………. 11 6.1 Command Summary ……………………………………………………………………………………………. 11

7. LCD Module Design and Handling Precautions……………………………………………………….. 14

8. CTP Mounting Instructions ……………………………………………………………………………………. 15

9. RTP Mounting Instructions ……………………………………………………………………………………. 16

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1. General Specification

Screen Size(Diagonal) : Resolution : Interface : Color Depth : Dot Pitch : Pixel Configuration : Display Mode : Surface Treatment : Viewing Direction : Outline Dimension : Active Area : Weight : Backlight : Operating Temperature : Storage Temperature :

3.5 inch 320(RGB) x 240 8bit MCU Interface 16.7M color (24bit) 0.219 x 0.219 (mm) RGB Stripe Transmissive / Positive Anti-Glare Treatment 12 o’clock 92.7 x 72.0 x 9.75 (mm) 70.08 x 52.56 (mm) Approx 54g LED, White -20 ~ +70°C -30 ~ +80°C

Note: Backlight color may slightly change over temperature and driving voltage.

2. Block Diagram

K1
D0 ~ D7 A0
/RES, /CS TE
/WR, /RD SPI_EN
BL_ADJ VDD VSS

S1D13L01 LCD Controller

Driver Config Serial I/F
Driver Display Signal

Power Circuit

Backlight Supply Figure 1

320(x3) x 240 pixels TFT Panel
TFT Driver Backlight Circuit

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2.1 Terminal Functions

Terminal (K1)

Pin Pin No. Name

I/O

1 2

VSS

Power Input

3 4

VDD

Power Input

Input

/CS

Input

/RES

Input

D0(SI)

D1(SO)

14 D6

Bi-directional I/O

15 D7

16 TE

Output

17 /RD

Input

/WR(SCK)

Input

19 BL_ADJ

Input

20 SPI_EN

22 23

Input –

8bit MCU Mode (Default) Description
Power Supply GND (0V)

SPI Mode Description

Positive Power Supply

Access Mode
A0=High: Accessing Data A0=Low: Accessing Address

Keep open

Chip Select
/CS=Low: Data IO is enabled

Reset
/RES=Low: Reset
/RES=High: Normal operation

8-bit Bi-directional data bus TE Signal

Serial input Serial output Keep open Keep open Keep open

Read Enable, active Low

Keep open

Write Enable, active Low

Serial clock

Backlight Driver enable signal, active High, PWM(*1) can be

possible

Keep open

SPI Enable, active high

No connect

Interface setting:
Setting
R5

8bit MCU Mode (Default) 0R(0603,5%)

SPI mode 10k(0603,5%)

Note: *1. The PWM frequency is between 200Hz and 500Hz.

3. Absolute Maximum Ratings

Items

Symbol Min. Max. Unit Condition

Supply Voltage

VDD

-0.2

3.7

VSS = 0V

Input Voltage

VIN

-0.2

3.7

VSS = 0V

Operating Temperature

TOP

-20 +70

No Condensation

Storage Temperature

TST

-30 +80

No Condensation

Caution:

Any Stresses exceeding the Absolute Maximum Ratings may cause substantial damage to the device. Functional

operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure

to extreme conditions may affect device reliability.

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4. Electrical Characteristics

4.1 DC Characteristics

Items Operating Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Operating Current

Symbol VDD VIH VIL VOH VOL IDD

MIN. 2.8
VSS 2.6
–

TYP. 3.3
145

MAX. 3.6 VDD 0.6 200

VSS=0V, VDD =3.3V, TOP =25
Unit Applicable Pin V VDD V Input pins, Bi-direction pins V Input pins, Bi-direction pins V Bi-direction pins (*1) V Bi-direction pins (*2) mA On Backlight Power on status

4.2 AC Characteristics 4.2.1 8080 Mode Timing

A0
/CS Control /CS /WR /RD
/RD,WR/ Control /CS /WR /RD

Figure 2

Symbol
t1 t2 t3 t4 t5w t5r t6 t7 t8 t9 t10w t10r t11w t12w

Parameter
A0 setup time to /CS (/WR, /RD) /WR, /RD (/CS) setup time to /CS (/WR, /RD) DB[7:0] setup time to /CS (/WR) rising edge: write cycle DB[7:0] hold time from /CS (/WR) rising edge: write cycle /WR (/CS) hold time from /CS (/WR) rising edge: write cycle /RD (/CS) hold time from /CS (/RD) rising edge: read cycle A0 hold time from /CS (/WR, /RD) rising edge /CS (/RD) falling edge to DB[7:0] driven: read cycle /CS (/RD) falling edge to valid Data: read cycle DB[7:0] hold time from /CS (/RD) rising edge: read cycle End of write to next read/write End of read to next read/write /CS (/WR) pulse width for write cycle /CS (/WR) rise to next /CS (/WR) rise: write cycle

Note: Tmclk = period of internal MCLK clock signal.

3.3 Volt

Min

Max

–

4xTmclk+17

–

Tmclk+9

–

3xTmclk+6

–

Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns

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Indirect 8-bit Function Select:

/WR

/RD

Comments Command Write (register address) Data (Parameter) Write inhibit Data (Parameter) Read

4.2.2 SPI Mode Timing

/CS

LMT035KDH03-NHN

Figure 3

Symbol
t1 t2 t3 t4 t5 t6 t7 t8 t9

Parameter
Chip select setup time SI Data setup time SI Data hold time Serial clock pulse width low (high) Serial clock pulse width high (low) Serial clock period Chip select hold time Chip select de-assert to reassert SCK falling edge to SO hold time

SPI Function Select: Command 10000000 11000000 10001000 11001000 the other

8-bit Write 8-bit Read 16-bit Write 16-bit Read reserved

Comments

3.3 Volt

Min

Max

–

Units
ns ns ns ns ns ns ns ns ns

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Write Procedure:
SPI 8bit Write Sequence:
/CS

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LMT035KDH03-NHN

SPI 16bit Write Sequence:
/CS

Figure 4

Read Procedure:
SPI 8bit Read Sequence:
/CS

Figure 5

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Figure 6
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SPI 16bit Read Sequence:
/CS

LCD Module User Manual

LMT035KDH03-NHN

Figure 7

4.2.3 Reset Timing

/RES

Figure 8

Symbol

Parameter

Min

Reset Pulse Width is ignored

–

Active Reset Pulse Width (see Note)

150

Note: The Reset input should be held low for longer than 150ns to guarantee reset.

Max

Units

–

For more information and details please refer to LCD controller (S1D13L01) datasheet.

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5. Optical Characteristics

LMT035KDH03-NHN

NoteThe parameter may slightly change over temperature, driving voltage and materials.

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Note 1: The data are measured after LEDs are turned on for 5 minutes. LCM displays full white. The brightness is the average value of 9 measured spots. Measurement equipment PR-705 (8mm) Measuring condition:
– Measuring surroundings: Dark room – Measuring temperature: Ta=25.
– Adjust operating voltage to get optimum contrast at the center of the display.
Measured value at the center point of LCD panel after more than 5 minutes while backlight turning on.

LMT035KDH03-NHN

Note 2: reference Figure5 The luminance uniformity is calculated by using following formula.
Bp = Bp (Min.) / Bp (Max.)×100 (%)
Bp (Max.) = Maximum brightness in 9 measured spots
Bp (Min.) = Minimum brightness in 9 measured spots.

Figure 9

Note 3: reference Figure6 The definition of viewing angle: Refer to the graph below marked by and
Note 4: The definition of contrast ratio (Test LCM using PR-705):
Contrast Luminance When LCD is at “White” state Ratio(CR)= Luminance When LCD is at “Black” state (Contrast Ratio is measured in optimum common electrode
voltage)

Figure 10

Note 5: reference Figure7 Definition of Response time. (Test LCD using DMS501): The output signals of photo detector are measured when the input signals are changed from “black” to “white”(falling time) and from “white” to “black”(rising time), respectively. The response time is defined as the time interval between the 10% and 90% of amplitudes.Refer to figure as below.

Figure 11

Note 6: reference Figure8 Definition of Color of CIE Coordinate and NTSC Ratio.

Color gamut:

Area of RGB triangle Area of NTSC triangle

X100%

Figure 12

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6. Function Specifications

6.1 Command Summary

Command

Parameter

HEX

A 0 /CS /WR D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

Descriptions

Power Save P1 60804 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Power Save Configuration Register

D[7:0] 1 0 0 n/a n/a n/a n/a n/a n/a Power Save Bit[1:0] = 00 , PSM0 mode

P2 D[15:8]

1 0 0 n/a

n/a

Bit[1:0] = 01 , PSM1 mode n/a Bit[1:0] = 1x , NMM mode

Software

P1 60806 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Software Reset Register(Write Only)

Reset

D[7:0] 1 0 0 n/a n/a n/a n/a n/a n/a n/a n/a

P2 D[15:8]

1 0 0 n/a

n/a

Softw Bit[8] = 0 , no effect in hardware n/a are Bit[8] = 1 , all registers are reset to default values

Reset

PLL Setting 0 P1 60810 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

PLL Setting Register 0

D[7:0]

PLL PLL Bit[0] = 0 , the PLL is disabled
1 0 0 n/a n/a n/a n/a n/a n/a Bypa Enabl Bit[0] = 1 , the PLL enabled

P2 D[15:8]

PLL

ss e Bit[1] = 0 , PLL is selected Bit[1] = 1 , CLKI is selected

1 0 0 Lock n/a n/a n/a n/a n/a n/a n/a Bit[15] = 0 , the PLL output is not stable

(RO)

Bit[15] = 1 , the PLL output is stable

PLL Setting 1 P1 60812 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

PLL Setting Register 1

D[7:0] 1 0 0 P2 D[15:8] 1 0 0 n/a n/a

M-Divider N-Counter

M-Divider

Bit[9:0] 000h,001h … … 019h,020h : 1:1 ,2:1 … … 33:1(M-Divide Ratio). 021h to 13Fh: Reserved, PFDCLK = CLKI ÷ (M-Divider + 1)
Bit[13:10] , must be set to 0000

PLL Setting 2 P1 60814 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

PLL Setting Register 2

D[7:0] D[15:8]

1 0 0 1 0 0 n/a

n/a

L-Counter n/a n/a

n/a

Bit[9:0] , must be set between 010h ~ 041h. , and get the M-Divide Ratio L-Counter from 17:1 to 66:1. POCLK = (L-Counter + 1) x (N-Counter + 1) x PFDCLK

Internal Clock P1 60816 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Internal Clock Configuration Register

Configuration

D[7:0] D[15:8]

1 0 0 n/a 1 0 0 n/a

n/a n/a

n/a PCLK Divide Select Bit[3:0] = 0000b,0001b … … 1110b,1111b : 1:1 ,2:1 … … 16:1(MCLK to n/a n/a n/a n/a PCLK Frequency Ratio)

Panel Setting P1 60820 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Panel Setting Miscellaneous Register

Miscellaneous

D[7:0]

PCLK DE Polarity Polari
ty

n/a

Panel Data Enabl
e

Panel Data Width

Panel Bit[0] = 0 , TFT panel is disable Port Bit[0] = 1 , TFT panel is enable Enabl Bit[2:1] = 01 , TFT 16-bit
e Bit[2:1] = 10 , TFT 18-bit

D[15:8]

Bit[2:1] = 11 , TFT 24-bit

Bit[3] = 0 , panel data is disable

Bit[3] = 1 , panel data is enable

Bit[5] = 0, the LCD data outputs transition on the rising edge of PCLK
1 0 0 n/a n/a n/a n/a n/a n/a n/a n/a Bit[5] = 1 , the LCD data outputs transition on the falling edge of PCLK
Bit[7:6] = 00 , DE Polarity Low active

Bit[7:6] = 01 , DE Polarity High active

Bit[7:6] = 10 , DE Polarity Fixed to Low

Bit[7:6] = 11 , DE Polarity Fixed to High

Display

P1 60822 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Display Settings Register

Settings

D[7:0]

TE Statu
s (RO)

Displ TE Function ay
Blank

Displ

Panel Bit[0] = 0 , HS, VS, DE and PCLK are fixed to H or L and the display pipes

ay SW Interf are disabled

n/a Blank Video ace Bit[0] = 1 , enable the panel output and display pipes

Polari Invert Enabl Bit[1] = 0 , video data is normal

es Bit[1] = 1 , video data is inverted

D[15:8]

Bit[2] = 0 , the display blank function operates normally

Bit[2] = 1 , the display blank function switches polarity

Bit[4] = 0 , the LCD data is masked

Bit[4] = 1 , all applicable LCD data outputs are forced to zero or one

1 0 0 n/a

n/a

TE Outp ut Pin Disab
le

Bit[6:5] = 00b , TE output is disabled and the pin output is low Bit[6:5] = 01b , TE output is high (1) when the display is in the Vertical Non-Display Period (VNDP) and low (0) when the display is in Vertical Display Period (VDISP) Bit[6:5] = 10b , Line Count Bit[6:5] = 11b , Reserved

Bit[7] = 0 , the selected condition in not occurring

Bit[7] = 1 , the selected condition in not occurring

Bit[8] = 0 , TE is output

Bit[8] = 1 , TE is not output

HDISP

P1 60824 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Horizontal Display Width Register (HDISP)

D[7:0] D[15:8]

1 0 0 n/a 1 0 0 n/a

n/a

Horizontal Display Width n/a n/a n/a n/a n/a

Bit[6:0] = horizontal display width in pixels ÷ 8 n/a

HNDP

P1 60826 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Horizontal Non-Display Period Register (HNDP)

D[7:0] D[15:8]

1 0 0 n/a 1 0 0 n/a

n/a

Horizontal Non-Display Period n/a n/a n/a n/a n/a

Bit[6:0] = horizontal non-display period in PCLK’s n/a

VDISP

P1 60828 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Vertical Display Height Register (VDISP)

D[7:0] 1 0 0

Vertical Display Height

P2 D[15:8] 1 0 0 n/a n/a n/a n/a n/a n/a

Vertical Bit[9:0] = vertical display height in lines Display

Height

VNDP

P1 6082A 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Vertical Non-Display Period Register (VNDP)

D[7:0] D[15:8]

1 0 0 1 0 0 n/a

Vertical Non-Display Period n/a n/a n/a n/a n/a n/a

Bit[7:0] = vertical non-display period in lines n/a

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Command

Parameter

HEX

A 0 /CS /WR D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

Descriptions

HSW

P1 6082C 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

HS Pulse Width Register (HSW)

D[7:0]

Pulse Polari

HS Pulse Width

Bit[6:0] = HS pulse width in PCLK’s Bit[7] = 0 , the horizontal sync signal is active low

Bit[7] = 1 , the horizontal sync signal is active high

D[15:8] 1 0 0 n/a n/a n/a n/a n/a n/a n/a n/a

HPS

P1 6082E 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

HS Pulse Start Position Register (HPS)

D[7:0] D[15:8]

1 1

0 0

n/a n/a

n/a

HS Pulse Start Position n/a n/a n/a n/a n/a

Bit[6:0] = HS pulse start position in PCLK’s n/a

VSW

P1 60830 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

VS Pulse Width Register (VSW)

D[7:0]

Pulse Polari

n/a

VS Pulse Width

Bit[5:0] = VS pulse width in lines Bit[7] = 0 , the vertical sync signal is active low

Bit[7] = 1 , the vertical sync signal is active high

D[15:8] 1 0 0 n/a n/a n/a n/a n/a n/a n/a n/a

VPS

P1 60832 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

VS Pulse Start Position Register (VPS)

D[7:0] D[15:8]

1 1

0 0

n/a

VS Pulse Start Position n/a n/a n/a n/a

n/a

Bit[7:0] = VS pulse start position in lines n/a

TE Line Count P1 60834 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

TE Line Count Register

D[7:0] 1 0 0

TE Line Count

P2 D[15:8] 1 0 0 n/a n/a n/a n/a n/a n/a

TE Line Count

These bits specify the line count value that is compared with the internal vertical line counter

Main Layer P1 60840 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Main Layer Setting Register

Setting

D[7:0]

1 0 0 n/a

D[15:8]

P2 1 0 0 n/a

n/a n/a

Main Layer n/a Rotation
Select
n/a n/a n/a

Main Layer Color

Depth

Bit[2:0] = 000b, RGB 8:8:8 (default)

n/a

MultiByte Layer Regis ters Sync hrono us Latch ing Disab

Bit[2:0] = 001b, RGB 5:6:5 Bit[2:0] = 010b/011b/111b, Reserved Bit[2:0] = 100b, 24 bpp + LUT1 Bit[2:0] = 101b, 16 bpp + LUT1 Bit[2:0] = 110b, 8 bpp + LUT1 Bit[4:3] = 00b, 0° (Normal) Bit[4:3] = 01b, 90° Bit[4:3] = 10b, 180° Bit[4:3] = 11b, 270° Bit[8] = 0, Synchronous latching of multi-byte layer Bit[8] = 1, Synchronous latching of multi-byte layer

registers registers

is is

enabled disabled

Main Layer P1 60842 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Main Layer Start Address Register 0

Start Address 0

D[7:0] D[15:8]

1 0 0 1 0 0

Main Layer Start Address Main Layer Start Address

Bit[15:0] is Bit[15:0] of Main Layer Start Address ,but Bit[1:0] must be set to 00b

Main Layer P1 60844 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Main Layer Start Address Register 1

Start Address

D[7:0]

1 0 0 n/a

n/a n/a

n/a

Main Layer Start

Address

Bit[2:0] is Bit[18:16] of Main Layer Start Address

D[15:8] 1 0 0 n/a n/a n/a n/a n/a n/a n/a n/a

Main Layer P1 60846 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Main Layer Width Register

Width

D[7:0] 1 0 0

Main Layer Width

P2 D[15:8] 1 0 0 n/a

n/a

Main Layer Read Only Width

Main Layer P1 60848 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Main Layer Height Register

Height

D[7:0] 1 0 0

Main Layer Height

P2 D[15:8] 1 0 0 n/a

n/a

Main Layer Read Only Height

PIP Layer P1 60850 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

PIP Layer Setting Register

Setting

D[7:0] 1 0 0 n/a n/a n/a n/a n/a n/a n/a n/a Bit[2:0] = 000b, RGB 8:8:8 (default)

D[15:8]

Bit[2:0] = 001b, RGB 5:6:5

Bit[2:0] = 010b/011b/111b, Reserved

Bit[2:0] = 100b, 24 bpp + LUT1

PIP Layer
1 0 0 n/a n/a n/a Rotation
Select

PIP Layer Color Depth

Bit[2:0] = 101b, 16 bpp + LUT1 Bit[2:0] = 110b, 8 bpp + LUT1 Bit[4:3] = 00b, 0° (Normal)

Bit[4:3] = 01b, 90°

Bit[4:3] = 10b, 180°

Bit[4:3] = 11b, 270°

PIP Layer P1 60852 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

PIP Layer Start Address Register 0

Start Address 0

D[7:0] D[15:8]

1 0 0 1 0 0

PIP Layer Start Address PIP Layer Start Address

Bit[15:0] is Bit[15:0] of Main Layer Start Address ,but Bit[1:0] must be set to 00b

PIP Layer P1 60854 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

PIP Layer Start Address Register 1

Start Address

D[7:0] 1 0 0 n/a n/a n/a n/a n/a n/a n/a n/a

P2 D[15:8] 1 0 0 n/a n/a n/a n/a n/a

PIP Layer Start Bit[2:0] is Bit[18:16] of Main Layer Start Address Address

PIP Layer P1 60856 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

PIP Layer Width Register

Width

D[7:0] 1 0 0 P2 D[15:8] 1 0 0 n/a

n/a

PIP Layer Width n/a n/a n/a n/a

Bit[9:] = PIP Layer Horizontal Display Period in number of pixels PIP PIP Layer Layer Horizontal Display Period in number of pixels
Width

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Command

Parameter

HEX

A 0 /CS /WR D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

Descriptions

PIP Layer Height
PIP Layer X Start Position

P1 60858 0 0 0 D[7:0] 1 0 0
P2 D[15:8] 1 0 0 n/a
P1 6085A 0 0 0 D[7:0] 1 0 0

A[7:0]-> A[15:8] -> A[18:16]

PIP Layer Height Register

PIP Layer Height

n/a

PIP Layer Bit[9:] = PIP Layer Vertical Display Period in number of lines Height

A[7:0]-> A[15:8] -> A[18:16]

PIP Layer X Start Position Register

PIP Layer X Start Position

PIP Layer Y Start Position

P2 D[15:8] 1 0 0 n/a
P1 6085C 0 0 0 D[7:0] 1 0 0

PIP Layer X These bits specify X start position of the PIP Layer on the panel, in lines

n/a n/a n/a n/a n/a

Start

Position

A[7:0]-> A[15:8] -> A[18:16]

PIP Layer Y Start Position Register

PIP Layer Y Start Position

PIP Enable

P2 D[15:8] 1 0 0 n/a P1 60860 0 0 0

PIP Layer Y These bits specify Y start position of the PIP Layer on the panel, in lines

n/a n/a n/a n/a n/a

Start

Position

A[7:0]-> A[15:8] -> A[18:16]

PIP Enable Register

Alpha Blending
Transparency

D[7:0]

1 0 0 n/a

D[15:8] P2 1 0 0

P1 60862 0 0 0 D[7:0] 1 0 0 n/a
D[15:8]

1 0 0 n/a

P1 60864 0 0 0

Blink/

Bit[2:0] = 000b, Blank

n/a

Fade Status

Blink/Fade Effect

Bit[2:0] = 001b, Normal Bit[2:0] = 010b, Blink 1

(RO)

Bit[2:0] = 011b, Blink 2

Bit[2:0] = 100b, Fade Out

Bit[2:0] = 101b, Fade In

Bit[2:0] = 110b, Fade In/Out Continuous

Blink/Fade Period

n/a Bit[2:0] = 111b, Reserved

Bit[3] = 0b, the PIP layer is not blinking or fading

Bit[3] = 1b, the PIP layer is in the process of blinking or fading

Bit[15:9] = blink/fade period in frames 1

A[7:0]-> A[15:8] -> A[18:16]

Alpha Blending Register

Alpha Blending Ratio

Bit[6:0] = 0000000b,0000001b… …0111111b,1000000b :

64:0 (no PIP),63:1 … … 1:63,0:64(full PIP) ;

n/a n/a n/a n/a n/a

Alpha Blending
Step

1000001b ~ 1111111b : Reserved Bit[9:8] = 00b, 1 Bit[9:8] = 01b, 2 Bit[9:8] = 10b, 4

Bit[9:8] = 11b, 8

A[7:0]-> A[15:8] -> A[18:16]

Transparency Register

D[7:0]

Transp

1 0 0 n/a n/a n/a n/a n/a n/a n/a arency Bit[0] = 0b, transparency is disabled
Enable Bit[0] = 1b, transparency is enabled

D[15:8] 1 0 0 n/a n/a n/a n/a n/a n/a n/a n/a

Transparency P1 60866 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Transparency Key Color Register 0

Key Color 0

D[7:0] D[15:8]

1 1

0 0

Key Color Blue Key Color Green

Bit[15:8] is Key Color Green bits [7:0] Bit[7:0] is Key Color Blue bits [7:0]

Transparency P1 60868 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

Transparency Key Color Register 1

Key Color 1

D[7:0] D[15:8]

1 1

0 0

n/a

Key Color Red n/a n/a n/a n/a

n/a

Bit[7:0] is Key Color Red bits [7:0] n/a

GPIO

P1 608D0 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

GPIO Configuration Register

Configuration

D[7:0] D[15:8]

1 1

0 0

0 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Bit[15:0] = 0b (default), the corresponding GPIO pin is configured as an
Config Config Config Config Config Config Config Config input pin
0 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 Bit[15:0] = 1b , the corresponding GPIO pin is configured as an output pin

Config Config Config Config Config Config Config Config

GPIO Status P1 608D2 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

GPIO Status and Control Register

and Control

D[7:0]

1 0 0 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 When GPIOx is configured as an output:

D[15:8]

Status Status Status Status Status Status Status
0 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9

Status Bit[15:0] = 0b, GPIOx low GPIO8 Bit[15:0] = 1b, GPIOx high

Status Status Status Status Status Status Status Status

GPIO Pull- P1 608D4 0 0 0

A[7:0]-> A[15:8] -> A[18:16]

GPIO Pull-Down Control Register

Down Control

D[7:0]

GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO 2 GPIO1 GPIO0

1 0 0 Pull-

Pull-

down down down down down down down down Bit[15:0] = 0b, the pull-down resistor for the associated GPIO pin is

P2 D[15:8]

Control Control Control Control Control Control Control Control inactive. GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 Bit[15:0] = 1b, the pull-down resistor for the associated GPIO pin is active.

1 0 0 Pull-

Pull-

down down down down down down down down

Control Control Control Control Control Control Control Control

Note: Access of PLL Setting 0, PLL Setting 1, PLL Setting 2 and Internal Clock Configuration is only possible in Power Save Mode PSM0.

For more information and details please refer to S1D13L01 datasheet.

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7. LCD Module Design and Handling Precautions
– Please ensure V0, VCOM is adjustable, to enable LCD module get
the best contrast ratio under different temperatures, view angles and positions.
– Normally display quality should be judged under the best contrast
ratio within viewable area. Unexpected display pattern may come out under abnormal contrast ratio.
– Never operate the LCD module exceed the absolute maximum
ratings.
– Never apply signal to the LCD module without power supply.
– Keep signal line as short as possible to reduce external noise
interference.
– IC chip (e.g. TAB or COG) is sensitive to light. Strong light might
cause malfunction. Light sealing structure casing is recommended.
– Make sure there is enough space (with cushion) between case and
LCD panel, to prevent external force passed on to the panel; otherwise that may cause damage to the LCD and degrade its display result.
– Avoid showing a display pattern on screen for a long time
(continuous ON segment).
– LCD module reliability may be reduced by temperature shock. – When storing and operating LCD module, avoids exposure to direct
sunlight, high humidity, high or low temperature. They may damage or degrade the LCD module.
– Never leave LCD module in extreme condition (max./min
storage/operate temperature) for more than 48hr.
– Recommend LCD module storage conditions is 0 C~40 C
<80%RH.
– LCD module should be stored in the room without acid, alkali and
harmful gas.
– Avoid dropping & violent shocking during transportation, and no
excessive pressure press, moisture and sunlight.
– LCD module can be easily damaged by static electricity. Please
maintain an optimum anti-static working environment to protect the LCD module. (eg. ground the soldering irons properly)
– Be sure to ground the body when handling LCD module. – Only hold LCD module by its sides. Never hold LCD module by
applying force on the heat seal or TAB.
– When soldering, control the temperature and duration avoid
damaging the backlight guide or diffuser which might degrade the display result such as uneven display.
– Never let LCD module contact with corrosive liquids, which might
cause damage to the backlight guide or the electric circuit of LCD module.
– Only clean LCD with a soft dry cloth, Isopropyl Alcohol or Ethyl
Alcohol. Other solvents (e.g. water) may damage the LCD.
– Never add force to components of LCD module. It may cause
invisible damage or degrade the module’s reliability.
– When mounting LCD module, please make sure it is free from
twisting, warping and bending.
– Do not add excessive force on surface of LCD, which may cause
the display color change abnormally.
– LCD panel is made with glass. Any mechanical shock (e.g.
dropping from high place) will damage the LCD module.

7.
– V0, VCOM ,

–
(V.A)
–
–

–

– IC ( TAB COG)

– (
)
–

– –

– (//)
48
– : 0 C~40 C <80%RH – , ,

– , ,
, , .
–
(: ,)
– –
TAB
–

–

– ,
(:)
–

–

– (
)

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– Protective film is attached on LCD screen. Be careful when peeling –

off this protective film, since static electricity may be generated.

– Polarizer on LCD gets scratched easily. If possible, do not remove –

LCD protective film until the last step of installation.

– When peeling off protective film from LCD, static charge may cause –

abnormal display pattern. The symptom is normal, and it will turn

back to normal in a short while.

– LCD panel has sharp edges, please handle with care.

–

– Never attempt to disassemble or rework LCD module.

–

– If display panel is damaged and liquid crystal substance leaks out, –

be sure not to get any in your mouth, if the substance comes into

contact with your skin or clothes promptly wash it off using soap

and water.

,
, ; , , , .

8. CTP Mounting Instructions
8.1 Bezel Mounting (Figure 1)
– The bezel window should be bigger than the CTP active area. It
should be0.5mm each side.
– Gasket should be installed between the bezel and the CTP surface.
The final gap should be about 0.5~1.0mm.
– It is recommended to provide an additional support bracket for
backside support when necessary (e.g. slim type TFT module
without mounding structure). They should only provide appropriate
support and keep the module in place.
– The mounting structure should be strong enough to prevent
external uneven force or twist act onto the module.

8. 8.1 1 – CTP
0.5mm.
– CTP 0.5
1.0mm.
– (
TFT ).
–
.

Figure 1
8.2 Surface Mounting (Figure 2)
– As the CTP assembling on the countersink area with double side
adhesive.
The countersink area should be flat and clean to ensure the double
side adhesive installation result.
– The Bezel is recommend to keep a gap (0.3mm each side)
around the cover lens for tolerance.
– It is recommended to provide an additional support bracket with
gasket for backside support when necessary (e.g. TFT module
without mounding structure). They should only provide appropriate
support and keep the module in place.
– The mounting structure should be strong enough to prevent
external uneven force or twist act onto the module

8.2 2
– CTP
.
– CTP
0.3mm .
– (
TFT ) .
–

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Figure 2

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8.3 Additional Cover Lens Mounting (Figure 3)
– For the case of additional cover Lens mounting, it is necessary to
recheck with the CTP specification about the material and thickness
to ensure the functionality.
– It should keep a 0.2~0.3mm gap between the cover lens and the
CTP surface..
– The cover lens window should be bigger than the active area of the
CTP.It should be0.5mm each side.
– It is recommended to provide an additional support bracket for
backside support when necessary (e.g. slim type TFT module
without mounding structure). They should only provide appropriate
support and keep the module in place.
– The mounting structure should be strong enough to prevent
external uneven force or twist act onto the module.

8.3 3
–
.
– CTP 0.20.3mm .
– CTP
0.5mm
– (
TFT ).
–
.

Figure 3

9. RTP Mounting Instructions
– It should bezel touching the RTP Active Area (A.A.) to prevent
abnormal touch.It should left gab D=0.2~0.3mm in between. (Figure 4)
– Outer bezel design should take care about the area outside the
A.A. Those areas contain circuit wires which is having different thickness. Touching those areas could de-form the ITO film. As a result bezel the ITO film be damaged and shorten its lifetime. It is suggested to protect those areas with gasket (between the bezel and RTP).The suggested figures are B0.50mm; C0.50mm. (Figure 4)
– The bezel side wall should keep space E= 0.2 ~ 0.3mm from the
RTP. (Figure 4)

9. – (A.A.)
(RTP) D=0.2~0.3mm .( 4)
–
ITO Film ITO RTP RTP Gasket V.A. B0.50mm; V.A. C0.50mm. ( 4)
– RTP RTP
E0.2mm. ( 4)

– In general design,
RTP V.A. should be bigger than the TFT V.A. and RTP A.A. should be bigger than the TFT A.A. (Figure 5)

Figure 4
–
RTP V.A. TFT V.A. RTP A.A. TFT A.A. ( 5)

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Figure 5
Warranty
This product has been manufactured to our company’s specifications as a part for use in your company’s general electronic products. It is guaranteed to perform according to delivery specifications. For any other use apart from general electronic equipment, we cannot take responsibility if the product is used in medical devices, nuclear power control equipment, aerospace equipment, fire and security systems, or any other applications in which there is a direct risk to human life and where extremely high levels of reliability are required. If the product is to be used in any of the above applications, we will need to enter into a separate product liability agreement.
– We cannot accept responsibility for any defect, which may arise form additional manufacturing of the product
(including disassembly and reassembly), after product delivery.
– We cannot accept responsibility for any defect, which may arise after the application of strong external force to the
product.
– We cannot accept responsibility for any defect, which may arise due to the application of static electricity after the
product has passed our company’s acceptance inspection procedures.
– When the product is in CCFL models, CCFL service life and brightness will vary according to the performance of the
inverter used, leaks, etc. We cannot accept responsibility for product performance, reliability, or defect, which may arise.
– We cannot accept responsibility for intellectual property of a third part, which may arise through the application of
our product to our assembly with exception to those issues relating directly to the structure or method of manufacturing of our product.

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