Diodes Evb1 100w Pfc+qr+gan Pd3.0 Adapter User Guide

100W PFC+QR+GaN PD3.0 Adapter
EVB1 User Guide

Summary

General Description

The 100W PD3.0 Evaluation Board (EVB1) is composed of four main controllers, AP33510, APR349, AP43771V and UCC28056B (TI). The AP33510, a highly integrated QuasiResonant (QR) controller with direct Enhancement-mode Gallium Nitride (E-Gann) driver integration, is optimally designed to meet ultra-low standby power and high power density (HPD) charger applications. The APR349, a secondary side synchronous rectifier (SR) controller, is adopted for efficiency optimization. The AP43771V, a PD3.0 PPS protocol controller, automatically manages the PD3.0 PPS attachment process for the attached USB Type C ® -equipped device under charge (DUC), regulates the feedback information of the charger to fulfill voltage and current requirements from DUC. By adopting growing popularity of E-Gann FETs, the 100W EVB1 exemplifies HPD charger design with system BOM optimization to meet market trend.

Key Features

1.2.1 System Key Features

• Quasi-Resonant operation for Critical E-GaN switch Operation and Efficiency Improvement Approaches
• Cost-Effective Implementation for HPD Chargers
• High-Voltage Startup low standby power (<20mW)
• Meets DOE VI and COC Tier 2 Efficiency Requirements
• USB Type-C Port – Support the Maximum Output of 100W PD3.0 PPS (3.3V to 21V@20mV/step, 50mA/step)
• SSR Topology Implementation with an Opto-coupler for Accurate Step Voltage / Current Control
• Low overall system BOM cost

1.2.2 AP33510 Key Features

• QR Fullback Topology with Valley-on and Valley lock
• High-Voltage Startup
• Embedded VCC LDO for VCCIN pin to Guarantee Wide Range Output Voltage
• Integration of Accurate E-Gann direct-driver
• Low Constant Output Current for Output Short
• Non-Audible-Noise QR Control
• Soft Start During Startup Process
• Frequency Foldback for High Average Efficiency
• Secondary Winding Short Protection with FOCP
• Frequency Dithering for Reducing EMI
• Integration of X-CAP Discharge Function
• Useful Pin fault protection: SENSE Pin Floating Protection/FB/Opto-Coupler Open/Short Protection
• Comprehensive System Protection Feature: VOVP/OLP/BNO/SOVP/SUVP

1.2.3 APR349 Key Features

• SR Works with CCM / DCM / QR operation modes
• Eliminate Resonant Ringing Interference
• Fewest External Components used

1.2.4 AP43771V Key Feature

• Support USB PD Rev 3.0 V1.2
• USB-IF PD3.0/PPS Certified TID 4312
• Qualcomm® Quick Charge™ 5 Certified: QC20201127203
• MTP for System Configuration
• OTP for Main Firmware
• Operating Voltage Range: 3.3V to 21V
• Built-In Regulator for CV and CC Control
• Programmable OVP/UVP/OCP/OTP
• Support Power Saving Mode
• External N-MOSFET Control for VBUS Power Delivery
• Supports E-Marker Cable Detection
• QFN-14 and QFN-24

1.3 Applications

• Quick Charger with PD3.0

1.4 Main Power Specifications

1.5 Evaluation Board Pictures

Power Supply Specification

Specification and Test Results

Compliance

Schematic

Board Schematic

Bill of Material (BOM)

* Note: GaN device spec can find in InnoScience website http://www.innoscience.com.cn/
Note: transphorm GaN device spec can find in transphorm website https://www.transphormchina.com/

Transformer Design

Windings	Wire Gauge		Turns	Start Pin		End Pin	Tape
Np	Φ0.15 2UEW*20P		29	1		2	2T
BOBBIN PIN Define:
Item		Test Condition			Rating
Primary Inductance		Pin1-2,all other windings open, measured at 100kHz / 1V			200uH+/- 5%
Note		Bobbin: ATQ2315 Core ATQ2315

3.4 Schematics Description
3.4.1 AC Input Circuit & Differential Filter
The Fuse F1 protects against over-current conditions which occur when some main components fails. The L4 and L5 are common-mode chocks for the common mode  noise suppression. The BD1 and BD2 are bridge rectifier which converts alternating current and voltage into direct current and voltage. The C4, C9, L1 are composed of the  Pi filter for filtering the differential switching noise back to AC source.

3.4.2 AP33510 PWM Controller
AP33510, a highly integrated Quasi-Resonant Fullback (QR) controller, integrates high-voltage start-up function through HV pin and X-capacitor discharging function. It also  integrates a VCC LDO circuit, which allows the LDO to regulate the wide range VCCL to an acceptable value. This makes the AP33510 an ideal candidate for wide range  output voltage applications such as USB PD3.0 PPS. With embedded E-Gann drive, the AP33510 provides a safe and accurate gate signal to control switch Q4 (GaN FET)  operations and achieve high-power density charger applications. At no load or light load, the AP33510 enters the burst mode to minimize standby power consumption.

3.4.3 APR349 Synchronous Rectification (SR) MOSFET Driver
As a high performance solution, the APR349 is a secondary-side SR controller to effectively reduce the secondary side rectifier power dissipation which works in both QR/DCM/CCM operation.

3.4.4 AP43771V PD 3.0 Decoder & Protection on/off N MOSFET and Interface to Power Devices
Few important pins provide critical protocol decoding and regulation functions in AP43771V:

1. CC1 & CC2 (Pin 11, 10): CC1 & CC2 (Configuration Channel 1 & 2) are defined by USB Type-C spec to provide the channel communication link between power source and sink device.
2. Constant Voltage (CV): The CV is implemented by sensing VFB (pin 8) and comparing with internal reference voltage to generate a CV compensation signal on the  OCDRV pin (pin 5). The output voltage is controlled by firmware through CC1/CC2 channel communication with the sink device.
3. Constant Current (CC): The CC is implemented by sensing the current sense resistor (RCS, 10mΩ, 1%, Low TCR) and compared with internal programmable reference  voltage. The output current is controlled by firmware through CC1/CC2 channel communication with the sink device.
4. Loop Compensation: R19 & C19 form the voltage loop compensation circuit, and C18 form the current loop compensation circuit.
5. OCDRV (Pin5): It is the key interface link from secondary decoder (AP43771V) to primary regulation circuit (AP33510). It is connected to Opto-coupler PC1 Pin 2  (Cathode) for feedback information based on all sensed CC1 & CC2 signals for getting desired Vbus voltage & current.
6. PWR_EN (Pin2) to N-MOSFET Gate: The pin is used to turn on/off N-MOSFET (Q1) to enable/disable voltage output to the Bus.

The Evaluation Board (EVB) Connections

4.1 EVB PCB Layout
Main Board – 1

Daughter Board

4.2 Quick Start Guide before Connection
1) Before starting the 100W EVB test, the end user needs to prepare the following tool, software and manuals.
For details, please consult USBCEE sales through below link for further information.
USBCEE PD3.0 Test Kit: USBCEE Power Adapter Tester. https://www.usbcee.com/product-details/4

USBCEE PAT Tester	GUI Display	USB-A to Micro-B Cable	Type-C Cable

Figure 6. Test Kit / Test Cables

1. Prepare a certified three-foot USB Type-C® cable and a Standard-A to Micro-B Cable.
2. Connect the AC inputs: L & N wires of EVB to AC power supply output “L and N “wires.
3. Ensure that the AC source is switched OFF or disconnected before the connection steps.
4. A type-C cable for the connection between EVB’s and Type-C receptacles of test kit.
5. Output of Type-C port & USB A-port are connected to E-load + & – terminals by cables.

Connection with E-Load

Testing the Evaluation Board

5.1 Input & Output Characteristics
5.1.1 Input Standby Power

5.1.2 Multiple Output Full Load Efficiency at Different AC Line Input Voltage

Efficiency vs AC Line At Board End

5.1.3 Multiple Output Average Efficiency at Different Loading Port-C PD3.0_PDO_20V / 5V Average Efficiency

Port-C PD3.0_PDO_9V / 15V Average Efficiency

5.2 Key Performance Waveforms
5.2.1 100W PD3.0 System Start-up Time

5.2.2 Q1 / Q2 MOSFET Voltage Stress at Full Load @264Vac
Primary side MOSFET : Q1 and Secondary side SR MOSFET- Q2

5.2.3 System Output Ripple & Noise with the Cable
Connect 47uF AL Cap and 104MLCC to the cable output unit in parallel

5.2.4 Dynamic load —-10% Load~90% Load, T=5mS, Rate=100mA/uS (PCB End)

Output Voltage Transition Time from High to Low

5.2.7 Thermal Testing
Output Condition : 20V/3.25A

BD1: Bridge Rectifier
Q4 : Primary Side High Voltage GaN FET
Q3 : Secondary Side Sync-Rectifier
Q2 : APFC High Voltage GaN FET
U1 : AP33510, QR Controller
U4 : APR349, Sync-Rectifier Controller

Note: Component temperature can be further optimized with various system design and thermal management approaches by manufacturers.

5.3 EMI (Conduction) Testing
115Vac testing results
Output Condition : 20V/5A

230Vac testing results
Output Condition : 20V/5A

IMPORTANT NOTICE

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100W PFC+QR+GaN PD3.0 PPS Adapter EVB1
Page 28 of 28 03/9/2023
Rev 1
www.diodes.com

References

• Diodes Incorporated - Analog, Discrete, Logic, Mixed-Signal
• Diodes Incorporated - Analog, Discrete, Logic, Mixed-Signal
• Innoscience-Home
• YAGEO(国巨)品牌介绍_YAGEO(国巨)产品采购/价格查询-立创商城
• muRata(村田)品牌介绍_muRata(村田)产品采购/价格查询-立创商城
• Important Notice
• Terms and Conditions of Sales
• Gallium Nitride (GaN) Power Devices - Transphorm
• USBCEE