M5stack M5core2 V1.1 Esp32 Iot Development Kit Owner's Manual (+ PDF)

The ESP32-D0WDQ6-V3 chip is a dual-core system with two Harvard
Architecture Xtensa LX6 CPUs. It has embedded memory, external
memory, and peripherals located on the data bus and/or the
instruction bus of these CPUs. The address mapping of the two CPUs
is symmetric, except for some minor exceptions. Multiple
peripherals in the system can access embedded memory via DMA.

TFT Screen

The TFT screen is a 2-inch color screen driven by ILI9342C with
a resolution of 320 x 240. It operates at a voltage range of
2.6~3.3V and has a working temperature range of -10~5°C.

Power Management Chip

The Power Management chip used is X-Powers’s AXP192. It operates
at an input voltage range of 2.9V~6.3V and supports a charging
current of 1.4A.

Functional Description

This chapter describes the various modules and functions of the
ESP32-D0WDQ6-V3 chip.

CPU and Memory

The ESP32-D0WDQ6-V3 chip features Xtensa single-/dual-core
32-bit LX6 microprocessors with a maximum speed of up to 600MIPS.
The CPU has 448 KB ROM, 520 KB SRAM, and an additional 16 KB SRAM
in RTC. It supports multiple flash/SRAM chips through QSPI.

Storage Description

The ESP32 supports multiple external QSPI flash and static
random access memory (SRAM) with hardware-based AES encryption for
user program and data protection.

The ESP32 accesses external QSPI Flash and SRAM through caching.
It can map up to 16 MB external Flash code space into the CPU,
supporting 8-bit, 16-bit, and 32-bit access, and code execution. It
can also map up to 8 MB external Flash and SRAM to the CPU data
space, supporting 8-bit, 16-bit, and 32-bit access. The Flash
supports only read operations, while the SRAM supports both read
and write operations.

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2020

V0.01

TABLE OF CONTENTS
1. OUTLINE ……………………………………………………………………….. 3 2. PIN DESCRIPTION ……………………………………………………………. 5
2.1. USB INTERFACE …………………………………………………………….5 2.2. GROVE INTERFACE ………………………………………………………….5 3. FUNCTIONAL DESCRIPTION………………………………………………… 6 3.1. CPU AND MEMORY …………………………………………………………6 3.2. STORAGE DESCRIPTION……………………………………………………..6
3.2.1. External Flash and SRAM …………………………………………..6 3.3. CRYSTAL ……………………………………………………………………6 3.4. RTC MANAGEMENT AND LOW POWER CONSUMPTION ……………………….7
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1.OUTLINE
M5Core2 1.1 is ESP32 board which based on ESP32-D0WDQ6-V3 chip, contained 2-inch TFT screen. The board is made of PC+ABC.
1.1 Hardware Composition
The hardware of CORE2: ESP32-D0WDQ6-V3 chip, TFT screen, Green LED, Button, GROVE interface, TypeC-to-USB interface, Power Management chip and battery.
ESP32-D0WDQ6-V3 The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory,external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs.With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning that they usethe same addresses to access the same memory. Multiple peripherals in the system can access embeddedmemory via DMA.
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TFT Screen is a 2-inch color screen driven ILI9342C with a resolution of 320 x 240.
Operating voltage range is 2.6~3.3V, working temperature range is -10~5 . Power Management chip is X-Powers’s AXP192. The operating voltage range is
2.9V~6.3V and the charging current is 1.4A. CORE2 equips ESP32 with everything needed for programming, everything needed
for operation and development
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2.PIN DESCRIPTION
2.1. USB INTERFACE
M5CAMREA Configuration Type-C type USB interface, support USB2.0 standard communication protocol.
2.2. GROVE INTERFACE
4p disposed pitch of 2.0mm M5CAMREA GROVE interfaces, internal wiring and GND, 5V, GPIO32, GPIO33 connected.
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3.FUNCTIONAL DESCRIPTION
This chapter describes the ESP32-D0WDQ6-V3 various modules and functions.
3.1. CPU AND MEMORY
Xtensa single-/dual-core32-bitLX6microprocessor(s), upto600MIPS (200MIPSforESP32-S0WD/ESP32-U4WDH, 400 MIPS for ESP32-D2WD):
448 KB ROM 520 KB SRAM 16 KB SRAM in RTC QSPI supports multiple flash/SRAM chips
3.2. STORAGE DESCRIPTION
3.2.1.External Flash and SRAM
ESP32 support multiple external QSPI flash and static random access memory (SRAM), having a hardware-based AES encryption to protect the user programs and data.
ESP32 access external QSPI Flash and SRAM by caching. Up to 16 MB external Flash code space is mapped into the CPU, supports 8-bit, 16-bit and 32-bit access, and can execute code. Up to 8 MB external Flash and SRAM mapped to the CPU data space, support for 8-bit, 16-bit and 32-bit access. Flash supports only read operations, SRAM supports read and write operations.
3.3. CRYSTAL
External 2 MHz~60 MHz crystal oscillator (40 MHz only for Wi-Fi/BT functionality)
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3.4. RTC MANAGEMENT AND LOW POWER CONSUMPTION
ESP32 uses advanced power management techniques may be switched between different power saving modes. (See Table 5).
– Active Mode: RF chip is operating. Chip may receive and transmit a sounding signal.
– Modem-sleep mode: CPU can run, the clock may be configured. Wi-Fi / Bluetooth baseband and RF
– Light-sleep mode: CPU suspended. RTC and memory and peripherals ULP coprocessor operation. Any wake-up event (MAC, host, RTC timer or external interrupt) will wake up the chip. – Deep-sleep mode: only the RTC memory and peripherals in a working state. WiFi and Bluetooth connectivity data stored in the RTC. ULP coprocessor can work. – Hibernation Mode: 8 MHz oscillator and a built-in coprocessor ULP are disabled. RTC memory to restore the power supply is cut off. Only one RTC clock timer located on the slow clock and some RTC GPIO at work. RTC RTC clock or timer can wake up from the GPIO Hibernation mode.
– related sleep mode: power save mode switching between Active, Modem-sleep, Light-sleep mode. CPU, Wi-Fi, Bluetooth, and radio preset time interval to be awakened, to ensure connection Wi-Fi / Bluetooth. – Ultra Low-power sensor monitoring methods: the main system is Deep-sleep mode, ULP coprocessor is periodically opened or closed to measure sensor data. The sensor measures data, ULP coprocessor decide whether to wake up the main system.
Functions in different power consumption modes: TABLE 5
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Any Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Note: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
–Reorient or relocate the receiving antenna.
–Increase the separation between the equipment and receiver.
–Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
–Consult the dealer or an experienced radio/TV technician for help.
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment .This equipment should be installed and operated with minimum distance 20cm between the radiator& your body.