Mixtile Blade 3 Single Board Computer User Manual

Mixtile Blade 3 Single Board Computer User Manual

MIXTILE - logoBlade 3 Single Board Computer
User Manual

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Version Date Changes Name 
12022-06-15First versionVT

Introduction

1.1 Product Description
The Mixtape Blade 3 is a low-cost, low-power SBC based on the next-generation Rockchip RK3588 CPU. It allows you to cluster numerous Mix tile Blade 3  SBCs to expand your deployment, making it ideal for quick development, AI application prototyping, and edge computing.
Out-of-the-box, Mix tile Blade 3 is a stacking computer with an inbuilt PCIe Gen3 edge connector that enables the integration of many high-performance hardware platforms into a tiny form factor.
That hardware, when combined, provides a network speed of up to 20 Gb/s and a memory bandwidth of up to 136 GB/s. A Mix tile Blade 3 cluster in a 19- inch 2U chassis can support up to 600 CPU cores and 1320 GHz of processing power while requiring less than 1500 W of power.

1.2 Package list

  • 1x Mix tile Blade 3 (heatsink installed)

1.3 Main Features

  • CPU: Rockchip Octa-core Cortex-A76/A55 SoC processor RK3588
  • NPU: Up to 6 TOPS
  • Memory: Up to 32 GB LPDDR4 memory and up to 256 GB eMMC storage
  • HDMI interface:
    • HDMI 2.1 output (8K @ 60 FPS or 4K @ 120 FPS)
    • HDMI 2.0 input (4K @ 60 FPS)
  • Video encoder: H.264/H.265 video encoder up to 8K @ 30 FPS
  • Video decoder: H.265/H.264/VP9 video decoder up to 8K @ 60 FPS
  • Display: 4-lane MIPI-CSI
  • Storage expansion:
    • 4-lane PCIe Gen 3 in U.2 port
    • SATA 3.0 in U.2 port
    • Micro-SD 3.0 flash socket
  • PCIe expansion: Mini-PCIe socket with PCIe Gen 2.1 and USB 2.0 support
  • Ethernet expansion: Dual 2.5 gigabit Ethernet ports
  • USB: Dual USB 3.2 Gen 1 Type-C ports with DisplayPort 1.4 A
  • GPIOs: 30-pin GPIO socket that can be used as Digital I/O, I²C, USB 2.0, TTL UART, SPI, I²S
  • Software support: Preload customized Debian 11, also support other Linux distributions and Android 12
  • Power: USB Type-C Port-1 Support USB PD 2.0 protocol (Optional: 12 V DC standard SATA power in via U.2 port)
  • Dimensions: 2.5-inch Pico-ITX form factor, 100 x 72 mm
  • Operating temperature: 0 to +80° C

1.4 Block diagram & Product Overview
1.4.1 Block Diagram
The Block diagram for the Blade 3 single-board computer is shown below with descriptions for each function.

MIXTILE Blade 3 Single Board Computer - Figure 1

1.4.2 Product Overview

MIXTILE Blade 3 Single Board Computer - Figure 2MIXTILE Blade 3 Single Board Computer - Figure 3

1.4.3Physical Dimensions

MIXTILE Blade 3 Single Board Computer - Figure 4

1.5 Key Component Specifications

The key component specifications are described below with relevant hardware information and developing notices. For more information, pin assignments and signal descriptions are listed in Chapter 2, Connectors & Pin Assignments.

1.5.1 Rockchip 3588
The Rockchip RK3588 ARM64 CPU contains many peripherals to support multi-purpose.

  • Octa Cortex-A76/A55 SoC processing cores
  • Core operating frequencies up to 2.4GHz
  • Neural Process Unit with processing performance up to 6 TOPS
  • Support 8k@60 FPS H.265/H.264/VP9 decoder; 8K@30 FPS H.264/H.265 encoder
  • Supports up to 32 GB LPDDR4 memory and up to 256 GB eMMC storage

The SDRAM is 32bits data width, 4 ranks LPDDR4 memory capacities from 4GBytes to 32GBytes.
The system flash memory supports eMMC 5.1 memory capacities from 32GBytes to 256GBytes.
The default memory setting is 4/16GBytes LPDDR4 and 32/128GBytes eMMC for Blade 3.

1.5.2 MicroSD Socket
The MicroSD socket accepts standard 11mm x 15mm Micro-SD cards with capacities up to 256GBytes. The 4bits data interface supports the SDMMC3.0  protocol. While the default boot setting is the eMMC Flash which can change to the MicroSD card.

1.5.3 Mini-PCIe Socket
The mini-PCIe is a PCI card interface with a small form factor that uses a standard 52-pin mini-PCIe socket. It also contains a USB 2.0 interface.
The mini-PCIe socket supports the module sizes of 3052.
The module supporting configuration, including power, reset, and interrupt signals, is under software control by Core 3588. Since each module needs specific configuration definitions, check the configuration setting before connecting the module.
USB Support
The mini-PCIe socket supports a standard USB 2.0 interface.

1.5.4 Gigabit Ethernet
The IEEE802.3 compliant Ethernet supports auto-negotiation of 10/100/1000/2500Mb half-duplex and full-duplex. The RGMII interface from the processor connects the 2.5GbE to an external PHY, RTL8125BG-CG. The RJ45 connector has some status and speed lights. The green light indicates that you are connected, and the flashing light indicates that data is being sent. The yellow light indicates 2500Mbps and is turned off for 10/100/1000Mbps.

1.5.5 Power Input
Power Delivery (PD)
The power port is a USB-C port that supports USB Power Delivery 2.0. A Power Delivery controller on board allows for a maximum power input of 20V @ 3A.
12V DC
DC power inputs from a DC SATA power via U.2 port require 12V @ 3A.

1.5.6 USB 2.0/3.0 Host Ports
The Blade 3 features two USB Type-C ports. Both ports can support the USB-OTG capability as well as DisplayPort via USB Type-C. DisplayPort over  USB Type-C enables the USB Type-C connector and cable to offer audio/video (AV) transfer via the DisplayPort interface.
It supports DisplayPort 1.4 and has a maximum resolution of 7680×4320@30Hz.
USB Type-C Port-1 supports USB PD2.0 but not USB 2.0 for ADB.
Although USB Type-C Port-0 does not support USB PD2.0, it does support USB 2.0 for ADB debugging and firmware updates.

1.5.7 Display Support
The video output processor supports the resolution from 1920×1080@60Hz to 7680×4320@60Hz.
The default main display is HDMI.
HDMI-OUT
HDMI display compliant HDMI 1.4 and HDMI 2.1 with HDCP 2.3. It supports up to 1920×1080@120Hz and 7680×4320@60Hz/3840×2160@120Hz resolution.
HDMI-IN
HDMI input compliant HDMI 1.4 and HDMI 2.0 with HDCP 2.3. It supports input sources up to 1920×1080@120Hz and 3840×2160@60Hz resolution.

1.5.8 U.2 Connector
The U.2 interface employs a 68-pin U.2 connector with a standard SATA 3.0 signal, a PCIe 3.0 X4 signal (four lanes PCIe 3.0), and 12V power input.

1.5.9 LEDs and Dip Switch
The power LED indicates the status of the power supply. There is one SPST four-position dip switch that can be used to determine the system booting mode of the Blade 3 board. Only one position can be turned ON at a time; please keep in mind that you cannot switch two positions to ON at the same time.
When position 1 is set to ON, the Blade 3 will boot from eMMC.
When position 2 is set to ON, the Blade 3 will boot from the MicroSD card.
When position 3 is turned ON, the Blade 3 will boot from SPI Flash.
When position 4 is activated, Blade 3 enters MaskROM mode for firmware development.
MIXTILE Blade 3 Single Board Computer - Figure 5

Connectors & Pin Assignments

The following section lists the interface connector pin assignments and pin types with corresponding signal descriptions. The interface connectors on Blade 3 are listed in the table below.

2.1 30-Pin Connector

Pin #Pin NamePin TypeInput/OutputSignal Description
1VCC_SVOPowerOutputPower supply for USB,5V output MAX 500mA.
2GNDPowerNAPower and signal reference ground.
3USB2O_HOSTO_DMLVDSBIUSB20 HOST PortO Data Minus
4I2S2_SDI_M1signalInput1252 data input
5USB2O_HOSTO_DPLVDSBIUSB20 HOST Port() Data Plus
6I2S2_SDO_M1signalOutputI2S2 data output
7GNDPowerNAPower and signal reference ground.
81252_MCLK_M1signalOutputI2S2 Master clock
9I2C5_SDA_M3signalEHI2C5 Bus Date
10I2S2_SCLK_M1signalBI1252 serial clock or BCLK
11I2C5_SCL_M3signalOutputI2C5 Bus clock
12I2S2_LRCK_MlsignalBI1252 Left/Right channel clock
13GNDPowerNAPower and signal reference ground.
14GNDPowerNAPower and signal reference ground.
15SPI4_MISO_M2signalInputSPI4 Master input,Slave output
16CAN2_RXsignalInputCAN2 receive data
17SPI4_MOSI_M2signalOutputSPI4 Master output, Slave input
18CAN2_TXsignalOutputCAN2 transmit data
19SPI4_CLK_M2signalOutputSPI4 clock
20GNDPowerNAPower and signal reference ground.
21SPI4_CSO_M2signalOutputSPI4 Chip Select 0
22GPIOO_BOsignalBIGPIO bank 0 port BO
23GPIOLA4signalBIGPIO bank 1 port A4
24SARADC_VIN7AnalogInputSAR AX Channel 7 input
25GNDPowerNAPower and signal reference ground.
26SARADC_VIN6AnalogInputSAR AX Channel 6 input
27PWM14signalBIPulse Width Modulation 14 input or output
28GNDPowerNAPower and signal reference ground.
29PWM15signalBIPulse Width Modulation 15 input or output
30VCC_3V330PowerOutputPower supply for peripheral, 3.3V output MAX 500mA.

2.2 Fan Connector

Pin #Pin NamePin TypeInput/OutputSignal Description
1VCC5V_FANPowerOutputPower supply for FAN,5V output MAX 400mA.Control by GPI03_CO
2GNDPowerNAPower reference ground.

2.3 Mini-PCIe

Pin #Pin NamePin TypeInput/OutputSignal Description
1MINIPCIE2O_WAKEN_3V3_LsignalInputWake-up the signal from the mini-PCIe device
2VCC3V3_MINIPCIEPowerOutputPower supply for the mini-PCIe device,3.3V output MAX 3A in all pins
3NCfloatNANo connected to this pin
4GNDPowerNAPower and signal reference ground.
5NCfloatNANo connected to this pin
6NCfloatNANo connected to this pin
7MINIPCIE2O_CLKREQN_3V3_LsignalInputPCIe2.0 Channel Reference clock request
8NCfloatNANo connected to this pin
9GNDPowerNAPower and signal reference ground.
10NCfloatNANo connected to this pin
11PCIE20_2_REFCLKNLVDSOutputPCIe20 Port2 differential clock Negative
12NCfloatNANo connected to this pin
13PCIE20_2_REFCLKPLVDSOutputPCIe20 Port2 differential clock Positive
14NCfloatNANo connected to this pin
15GNDPowerNAPower and signal reference ground.
16NCfloatNANo connected to this pin
17NCfloatNANo connected to this pin
18GNDPowerNAPower and signal reference ground.
19NCfloatNANo connected to this pin
20W_DISABLENsignalOutputPCI-E device wireless disable
21GNDPowerNAPower and signal reference ground.
22MINIPCIE2O_PERSTNsignalOutputPCI-E devise reset
23PCIE20_2_RXNLVDSInputPCIe20 receives differential Negative
24VCC3V3_MINIPCIEPowerOutputPower supply for the mini-PCIe device,3.3V output MAX 3A in all pins
25PCIE20_2_RXPLVDSInputPCIe20 receives differential Positive
26GNDPowerNAPower and signal reference ground.
27GNDPowerNAPower and signal reference ground.
28NCfloatNANo connected to this pin
29GNDPowerNAPower and signal reference ground.
30NCfloatNANo connected to this pin
31MINIPCIE2O_TX_NLVDSOutputPCIe20 transmit differential Negative
32NCfloatNANo connected to this pin
33MINIPCIE2O_TX_PLVDSOutputPCIe20 transmit differential Positive
34GNDPowerNAPower and signal reference ground.
35GNDPowerNAPower and signal reference ground.
36MINIPCIE_USB_DMLVDSBIUSB20 HOST Portal Data Minus
37GNDPowerNAPower and signal reference ground.
38MINIPCIE_USB_DPLVDSBIUSB20 HOST Portal Data Plus
39VCC3V3_MINIPCIEPowerOutputPower supply for the mini-PCIe device,3.3V output MAX 3A in all pins
40GNDPowerNAPower and signal reference ground.
41VCC3V3_MINIPCIEPowerOutputPower supply for the mini-PCIe device,3.3V output MAX 3A in all pins
42NCfloatNANo connected to this pin
43GNDPowerNAPower and signal reference ground.
44NCfloatNANo connected to this pin
45NCfloatNANo connected to this pin
46NCfloatNANo connected to this pin
47NCfloatNANo connected to this pin
48NCfloatNANo connected to this pin
49NCfloatNANo connected to this pin
50GNDPowerNAPower and signal reference ground.
51NCfloatNANo connected to this pin
52VCC3V3_MINIPCIEPowerOutputPower supply for the mini-PCIe device,3.3V output MAX 3A in all pins

2.4 MIPI-CSI

Pin #Pin NamePin TypeInput/OutputSignal Description
1GNDPowerNAPower and signal reference ground.
2MIPI_CSIO_RX_DONLVDSInputMIPI CSIO receives differential data lane 0 Negative
3MIPI_CSIO_RX_DOPLVDSInputMIPI CSIO receives differential data lane 0 Positive
4GNDPowerNAPower and signal reference ground.
5MIPI_CSIO_RX_D1NLVDSInputMIPI CSIO receives differential data lane 1 Negative
6MIPI_CSIO_RX_D1PLVDSInputMIPI CSIO receives differential data lane 1 Positive
7GNDPowerNAPower and signal reference ground.
8MIPI_CSIO_RX_CLKONLVDSInputMIPI CSIO receives differential Clock 0 Negativ€
9MIPI_CSIO_RX_CLKOPLVDSInputMIPI CSIO receives differential Clock 0 Positive
10GNDPowerNAPower and signal reference ground.
11MIPI_CSIO_RX_D2NLVDSInputMIPI CSIO receives differential data lane 2 Negative
12MIPI_CSIO_RX_D2PLVDSInputMIPI CSIO receives differential data lane 2 Positive
13GNDPowerNAPower and signal reference ground.
14MIPI_CSIO_RX_D3NLVDSInputMIPI CSIO receives differential data lane 3 Negative
15MIPI_CSIO_RX_D3PLVDSInputMIPI CSIO receives differential data lane 3 Positive
16GNDPowerNAPower and signal reference ground.
17MIPI_CAM_PWM2signalOutputPWM2 for LENS
18NCfloatNANo connected to this pin
19VCC_3V3_S0PowerOutputPower supply for sensor board,3.3V output
20MIPI_CAM_RESETNsignalOutputGPIO out for sensor reset
21NCfloatNANo connected to this pin
22MIPI_CAM_PDNsignalOutputGPIO out for sensor power down
23I2C3_SDA_M3_MIPIsignalIllI2C5 Bus data
24I2C3_SCL_M3_MIPIsignalOutputI2C5 Bus clock
25GNDPowerNAPower and signal reference ground.
26MIPI_CAM2_CLK_M1_3V3signalOutputCamera Master clock output
27GNDPowerNAPower and signal reference ground.
28VCC_SVOPowerOutputPower supply for sensor board, SV output
29VCC_SVOPowerOutputPower supply for sensor board, SV output
30VCC_SVOPowerOutputPower supply for sensor board, SV output

2.5 U.2

Pin#Pin NamePin TypeInput/OutputSignal Description
ElPCIE30 REFCLKP SLOTLVDSOutputRC PCIe30 differential clock Positive
E2PCIE3O_REFCLKN_SLOTLVDSOutputRC PCIe30 differential clock Negative
E3VCC_3V3_SOPowerOutputPower supply for JO
E4PCIE30X4 CLKREQN_Ml_LsignalOutputDM PCIe30 Channel Reference clock request
E5PCIE30X4 PERSTN_MULsignalInputDM PCIe30 Channel reset
E6PCIE30X4 CLKREQN_M3signalInputRC PCIe30 Channel Reference clock request
E7PCIE30 PORT1 REFCLKPLVDSInputDM PCIe30 differential clock Positive
E8PCIE3O_PORTl_REFCLKNLVDSInputDM PCIe30 differential clock Negative
E9GNDPowerNAPower and signal reference ground.
E10PCIE3O_PORTl_TX2PLVDSOutputDM PCIe30 transmit differential Positive
E11PCIE30 PORT1 TX2NLVDSOutputDM PCIe30 transmit differential Negative
E12GNDPowerNAPower and signal reference ground.
E13PCIE30 PORT1 RX2NLVDSInputDM PCIe30 receives differential Negative
E14PCIE30 PORT1 RX2PLVDSInputDM PCIe30 receives differential Positive
E15GNDPowerNAPower and signal reference ground.
E16NCfloatNANo connected to this pin
E17PCIE30 PORTO RX1PLVDSInputRC PCIe30 receives differential Negative
E18PCIE30 PORTO RX1NLVDSInputRC PCIe30 receives differential Positive
E19GNDPowerNAPower and signal reference ground.
E20PCIE30 PORTO TX1NLVDSOutputRC PCIe30 transmit differential Positive
E21PCIE30 PORTO TX1PLVDSOutputRC PCIe30 transmit differential Negative
E22GNDPowerNAPower and signal reference ground.
E23I2C4 SCL MOsignalOutputI2C4 Bus clock
E24I2C4 SDA MOsignalBII2C4 Bus data
E25DUALPORT_EN#signalOutputGPIO for Enable dual port, default low
P1PCIE30X4_WAKEN_M l_LsignalOutputDM PCIE30 Wake-up signal from RC
P2PCIE30X4_WAKEN_M3signalInputRC PCIE30 Wake up the signal from DM
P3PWRDISsignalOutputGPIO for power disable to device
P4IFDETsignalInputGPIO for detecting the interface of the device
P5GNDPowerNAPower and signal reference ground.
P6GNDPowerNAPower and signal reference ground.
P7NCfloatNANo connected to this pin
P8NCfloatNANo connected to this pin
P9NCfloatNANo connected to this pin
P10PRSNT#signalInputGPIO for detecting device if present
P11ACTIVITY#signalInputGPIO for detecting device if the activity
P12GNDPowerNAPower and signal reference ground.
P13U2_12VPowerInputPower supply for blade3, input 12V
P14U2_12VPowerInputPower supply for blade3, input 12V
P15U2_12VPowerInputPower supply for blade3, input 12V
S1GNDPowerNAPower and signal reference ground.
S2SATAO TXPLVDSOutputSATA30 Port() transmit differential Positive
S3SATAO TXNLVDSOutputSATA30 Port() transmit differential Negative
S4GNDPowerNAPower and signal reference ground.
S5SATAO RXNLVDSInputSATA30 Port() receive differential Positive
S6SATAO RXPLVDSInputSATA30 Port() receive differential Negative
S7GNDPowerNAPower and signal reference ground.
S8GNDPowerNAPower and signal reference ground.
S9NCfloatNANo connected to this pin
S10NCfloatNANo connected to this pin
S11GNDPowerNAPower and signal reference ground.
S12NCfloatNANo connected to this pin
S13NCfloatNANo connected to this pin
S14GNDPowerNAPower and signal reference ground.
S15PCIE30X4_PERSTN_M3signalOutputRC PCIe30 Channel reset
S16GNDPowerNAPower and signal reference ground.
517PCIE30 PORTl_TX3PLVDSOutputDM PCIe30 transmit differential Negative
518PCIE30 PORTl_TX3NLVDSOutputDM PCIe30 transmit differential Positive
519GNDPowerNAPower and signal reference ground.
S20PCIE30 PORT1 RX3NLVDSInputDM PCIe30 receives differential Negative
S21PCIE30 PORT1 RX3PLVDSInputDM PCIe30 receives differential Positive
S22GNDPowerNAPower and signal reference ground.
S23PCIE30 PORTO RXOPLVDSInputRC PCIe30 receives differential Negative
S24PCIE30 PORTO RONLVDSInputRC PCIe30 receives differential Positive
S25GNDPowerNAPower and signal reference ground.
S26PCIE30 PORTO_TXONLVDSOutputRC PCIe30 transmit differential Negative
S27PCIE30 PORTO_TXOPLVDSOutputRC PCIe30 transmit differential Positive
S28GNDPowerNAPo+A137:E196wer and signal reference ground.

2.6 Debug

Pin#Pin NamePin TypeInput/OutputSignal Description
1UART2_RX_MO_DEBUGsignalInputUART2 Receive Data for debug
2UART2_TX_MO_DEBUGsignalOutputUART2 Transmit Data for debug
3GNDsignalNASignal reference ground.

Specifications

3.1 Environmental

ParameterSpecifications
Operating Temperature0 ° to +80 °C
Storage Temperature0 ° to +80 °C

3.2 Mechanical

Parameter Specifications 
2.5-inch Pico-ITX100 x 72mm
Weight160g

Support

4.1 Technical Support
MIX TILE technical support team assists you with the questions you may have. Contact us with the following methods below.
Email: [email protected]
Website: https://www.mixtile.com

References

Documents / Resouces

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